Changes between Version 1 and Version 2 of WARPLab/HardwareConfiguration

Timestamp:

May 13, 2013, 2:55:41 PM (11 years ago)

Author:

welsh

Comment:

--

WARPLab/HardwareConfiguration

@@ -7 +7 @@
 
 
-== Hardware Platform ==
+== WARP v3 ==
 
-=== WARP v2 ===
+[[Image(WARP_v3_labelled.png)]]
 
 
-=== WARP v3 ===
+=== Radio Interface ===
+
+  * In the 2 RF Node configuration (ie only RF A and RF B are populated), you '''cannot''' use the 4RF bitstream.
+  * In the 4 RF Node configuration (ie all RF interfaces are populated), you can use both the 4RF and 2RF bitstreams depending on how many of the RF interfaces you want to use. 
+
+
+=== Dip Switches ===
+
+  * In WARPLab 7.1 and later, the dip switch value of 0xF (ie all switches set to '1'), is reserved for [wiki:WARPLab/Reference/NodesConfig dynamic node configuration].
+
+
+=== Debug Header ===
+
+The [wiki:HardwareUsersGuides/WARPv3/DebugHeader debug header] is configured by default to map to the following pins:
+
+
+{{{
+# Debug Header defined in system.ucf
+
+NET "DEBUGHDR<0>"      LOC = "AG27"  | IOSTANDARD = "LVCMOS25";            #pin 0  - Capture tracking
+NET "DEBUGHDR<1>"      LOC = "AE26"  | IOSTANDARD = "LVCMOS25";            #pin 1  - Transmit tracking
+
+NET "debug_sw_gpio<0>" LOC = "AF26"  | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 2  - SW debug pin 0
+NET "debug_sw_gpio<1>" LOC = "AD25"  | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 3  - SW debug pin 1
+NET "debug_sw_gpio<2>" LOC = "V24"   | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 4  - SW debug pin 2
+NET "debug_sw_gpio<3>" LOC = "AA23"  | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 5  - SW debug pin 3
+NET "debug_sw_gpio<4>" LOC = "AH30"  | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 6  - SW debug pin 4
+NET "debug_sw_gpio<5>" LOC = "AK31"  | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 7  - SW debug pin 5
+
+NET "trigger_out<0>"   LOC = "AG28"  | IOSTANDARD = "LVCMOS25";            #pin 8  - Trigger output D0
+NET "trigger_out<1>"   LOC = "AE27"  | IOSTANDARD = "LVCMOS25";            #pin 9  - Trigger output D1
+NET "trigger_out<2>"   LOC = "AF28"  | IOSTANDARD = "LVCMOS25";            #pin 10 - Trigger output D2
+NET "trigger_out<3>"   LOC = "AJ29"  | IOSTANDARD = "LVCMOS25";            #pin 11 - Trigger output D3
+
+NET "trigger_in<0>"    LOC = "AH29"  | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 12 - Trigger input D0
+NET "trigger_in<1>"    LOC = "AL30"  | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 13 - Trigger input D1
+NET "trigger_in<2>"    LOC = "AM31"  | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 14 - Trigger input D2
+NET "trigger_in<3>"    LOC = "AP32"  | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 15 - Trigger input D3
+
+}}}
+
+{{{
+# Debug Header default connections in system.mhs
+
+# DEBUG
+ PORT debughdr      = warplab_mimo_4x4_plbw_0_debug_capturing & warplab_mimo_4x4_plbw_0_debug_transmitting, DIR = O, VEC = [1:0]
+ PORT debug_sw_gpio = debug_sw_gpio, DIR = IO, VEC = [5:0]
+ PORT trigger_in    = trig_0_in  & trig_1_in  & trig_2_in  & trig_3_in,  DIR = I, VEC = [0:3]
+ PORT trigger_out   = trig_2_out & trig_3_out & trig_4_out & trig_5_out, DIR = O, VEC = [0:3]
+
+}}}
+
+
+=== Clock Configuration ===
+
+  * Detailed information on the WARP v3 Clocking configuration can be found [wiki:HardwareUsersGuides/WARPv3/Clocking here].
+  * To adjust the [wiki:HardwareUsersGuides/CM-MMCX MMCX Clock Module] functionality, please use the following SIP switch settings:
+
+[[Image(MMCX_v1_labelled.png)]]
+
+
+=== Ethernet ===
+
+  * By default, only Ethernet connection A (Eth A) is used.
 
 
 
-== Radio Interface ==
-
-=== WARP v2 ===
-
-  * In the 2RF Node configuration
+== WARP v2 ==
 
 
-=== WARP v3 ===
+=== Radio Interface ===
 
+=== Dip Switches ===
 
+=== Debug Header ===
 
-== Dip Switches ==
+=== Clock Configuration ===
 
-=== WARP v2 ===
+=== Ethernet ===
 
-
-
-=== WARP v3 ===
-
-
-
-
-== Debug Header ==
-
-=== WARP v2 ===
-
-
-
-=== WARP v3 ===
-
-
-
-
-== Clock Configuration ==
-
-=== WARP v2 ===
-
-
-
-=== WARP v3 ===
-
-
-
-
-== Ethernet ==
-
-=== WARP v2 ===
-
-
-
-=== WARP v3 ===
-