| 6 | | == System Requirements == |
| 7 | | * Review the [wiki:../Requirements WARPLab 7 System Requirements] |
| 8 | | |
| 9 | | |
| 10 | | == WARP v3 == |
| 11 | | |
| 12 | | [[Image(WARP_v3_labelled.png)]] |
| 13 | | |
| 14 | | |
| 15 | | === Radio Interface === |
| 16 | | |
| 17 | | * In the 2 RF Node configuration (ie only RF A and RF B are populated), you should only use the '''2RF bitstream''' in the [wiki:WARPLab/Downloads download]. |
| 18 | | * In the 4 RF Node configuration (ie all RF interfaces are populated), you should only use the '''4RF bitstream''' in the [wiki:WARPLab/Downloads download]. |
| 19 | | |
| 20 | | |
| 21 | | === Dip Switches === |
| 22 | | |
| 23 | | * In WARPLab 7.1 and later, the dip switch value of 0xF (ie all switches set to '1'), is reserved for [wiki:WARPLab/Reference/NodesConfig dynamic node configuration]. |
| 24 | | |
| 25 | | |
| 26 | | === Debug Header === |
| 27 | | |
| 28 | | The [wiki:HardwareUsersGuides/WARPv3/DebugHeader debug header] is configured by default to map to the following pins: |
| 29 | | |
| 30 | | |
| 31 | | [[Image(Debug_Header_Diagram.png)]] |
| 32 | | |
| 33 | | || [[Image(wiki:HardwareUsersGuides/WARPv3/files:important.png,nolink,valign=middle)]] || '''These pins are not 3.3v compatible! ''' You must use external level shifting to interface with non-2.5v signals. || |
| 34 | | |
| 35 | | [[Image(Debug_Header_Connections.png)]] |
| 36 | | |
| 37 | | '''NOTE:''' The Debug Header is defined in the system.ucf and the connections are defined in the system.mhs |
| 38 | | |
| 39 | | * The Trigger output and Trigger input pins above are used with the [wiki:WARPLab/Reference/TriggerManager Trigger Manager] |
| 40 | | |
| 41 | | |
| 42 | | === Clock Configuration === |
| 43 | | The WARPLab reference design does not require any external clock connections. By default the reference design will use the oscillators on the WARP v3 board for all system and RF clocking. |
| 44 | | |
| 45 | | The reference design does support both sourcing and sinking external clocks for synchronization of multiple nodes. The WARP v3 kit must be equipped with a CM-MMCX clock module to source/sink clocks. The role of each node is configured via the 2-position SIP switch on the CM-MMCX, according to the figure below. |
| 46 | | |
| 47 | | * Detailed information on the WARP v3 Clocking configuration can be found [wiki:HardwareUsersGuides/WARPv3/Clocking here]. |
| 48 | | * To adjust the [wiki:HardwareUsersGuides/CM-MMCX MMCX Clock Module] functionality, please use the following SIP switch settings: |
| 49 | | |
| 50 | | [[Image(MMCX_v1_labelled.png)]] |
| 51 | | |
| 52 | | |
| 53 | | === Ethernet === |
| 54 | | |
| 55 | | * By default, only Ethernet connection A (Eth A) is used. |
| 56 | | |
| 57 | | |
| 58 | | |
| 59 | | == WARP v2 == |
| 60 | | |
| 61 | | [[Image(WARP_v2_labelled.png)]] |
| 62 | | |
| 63 | | |
| 64 | | === Radio Interface === |
| 65 | | |
| 66 | | * In the 2 RF Node configuration (ie only RF A and RF B are populated), you should only use the '''2RF bitstream''' in the [wiki:WARPLab/Downloads download]. |
| 67 | | * In the 4 RF Node configuration (ie all RF interfaces are populated), you should only use the '''4RF bitstream''' in the [wiki:WARPLab/Downloads download]. |
| 68 | | |
| 69 | | === Debug Header === |
| 70 | | |
| 71 | | The [wiki:HardwareUsersGuides/FPGABoard_v2.2/OtherIO#DigitalIO debug header] is configured by default to map to the following pins: |
| 72 | | |
| 73 | | [[Image(Debug_Header_Diagram_BnW.png)]] |
| 74 | | |
| 75 | | |
| 76 | | === Clock Configuration === |
| 77 | | |
| 78 | | * Detailed information on the WARP v2 Clocking configuration can be found [wiki:HardwareUsersGuides/FPGABoard_v2.2/Clocking here]. |
| 79 | | * To adjust the [wiki:HardwareUsersGuides/ClockBoard_v1.1] |
| 80 | | |
| 81 | | |
| 82 | | === Ethernet === |
| 83 | | |
| 84 | | * Only one Ethernet connection (Eth A) on the board |
| | 6 | * [wiki:./WARPv3 WARP v3] |
| | 7 | * [wiki:./WARPv2 WARP v2] |
