Changes between Version 1 and Version 2 of WARPLab/Reference/TriggerManager


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Timestamp:
May 13, 2013, 4:10:16 PM (11 years ago)
Author:
welsh
Comment:

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  • WARPLab/Reference/TriggerManager

    v1 v2  
    88== Overview ==
    99
     10The Trigger Manager was designed to allow flexible coordination and communication between nodes.  Each trigger is assigned an ID and then all configuration of the trigger manager is based on these IDs.  By default, WARPLab has the following triggers:
    1011
     12* Input
     13  * Ethernet
     14  * Input Energy
     15  * Automatic Gain Control (AGC) Done
     16  * Register writes (for WARP v2 compatibility)
     17  * External Pins (D0 - D3, pins 12 - 15 on the [wiki:WARPLab/HardwareConfiguration#DebugHeader debug header]).
     18
     19* Output
     20  * Baseband
     21  * Automatic Gain Control (AGC) Start
     22  * External Pins (D0 - D3, pins 8 - 11 on the [wiki:WARPLab/HardwareConfiguration#DebugHeader debug header]).
     23
     24The Trigger Manager allows a node to output triggers based on a logical combination of events on the node as well as perform operations based on a logical combination of input triggers to the node. 
     25
     26
     27TODO: BLOCK DIAGRAM
    1128
    1229
     
    1431== Hardware Setup ==
    1532
     33  The Trigger Manager consists of both a hardware block that runs within the FPGA and a [wiki:WARPLab/Reference/Commands/TriggerManager software framework] to configure and use the Trigger Manager.  You can see the instantiation of the Trigger Manager block as well as the default connections within the system.mhs file:
     34
     35{{{
     36# Default configuration of the Trigger Manager in system.mhs
     37
     38BEGIN w3_warplab_trigger_proc_axiw
     39 PARAMETER INSTANCE   = warplab_trigger_proc
     40 PARAMETER HW_VER     = 1.01.a
     41 PARAMETER C_BASEADDR = 0x77800000
     42 PARAMETER C_HIGHADDR = 0x7780ffff
     43 BUS_INTERFACE S_AXI  = axi4lite_1
     44 BUS_INTERFACE AXI_STR_ETH_RXD = ETH_A_AXI_STR_RXD
     45 PORT axi_aclk        = clk_160MHz
     46 PORT sysgen_clk      = clk_160MHz
     47 # Triggers
     48 PORT agc_done_in = agc_is_done
     49 PORT debug_0_in  = trig_0_in
     50 PORT debug_1_in  = trig_1_in
     51 PORT debug_2_in  = trig_2_in
     52 PORT debug_3_in  = trig_3_in
     53 PORT rfa_rssi    = warplab_rfa_rssi
     54 PORT rfb_rssi    = warplab_rfb_rssi
     55 PORT rfc_rssi    = net_gnd
     56 PORT rfd_rssi    = net_gnd
     57 PORT rssi_clk    = warplab_rssi_clk
     58 PORT trig_0_out  = baseband_trigger
     59 PORT trig_1_out  = agc_start
     60 PORT trig_2_out  = trig_2_out
     61 PORT trig_3_out  = trig_3_out
     62 PORT trig_4_out  = trig_4_out
     63 PORT trig_5_out  = trig_5_out
     64END
     65}}}
     66
     67The ''trig_*_in'' and ''trig_*_out'' signals are connected to the [wiki:WARPLab/HardwareConfiguration#DebugHeader debug header] and can be used to externally trigger events.
     68
     69
     70== Examples ==
     71
     72In our example, we have two nodes, a transmitter ( nodes(1) ) and a receiver ( nodes(2) ):
     73
     74* Create a UDP broadcast trigger and primary node to be ready for it
     75{{{
     76eth_trig = wl_trigger_eth_udp_broadcast;
     77}}}
     78
     79* Trigger the transmitting node with an Ethernet trigger
     80{{{
     81nodes(1).wl_triggerManagerCmd('add_ethernet_trigger',[eth_trig]);
     82}}}
     83  '''NOTE:'''  This will allow a host, like Matlab, to create an Ethernet packet to begin transmission 
     84
     85* Read Trigger IDs into workspace
     86{{{
     87[T_IN_ETH,T_IN_ENERGY,T_IN_AGCDONE,T_IN_REG,T_IN_D0,T_IN_D1,T_IN_D2,T_IN_D3] =  wl_getTriggerInputIDs(nodes(1));
     88[T_OUT_BASEBAND, T_OUT_AGC, T_OUT_D0, T_OUT_D1, T_OUT_D2, T_OUT_D3] = wl_getTriggerOutputIDs(nodes(1));
     89}}}
     90  '''NOTE:'''  These trigger IDs will be the same for all nodes in the system unless modified by the user.
     91
     92* For the transmit node, we will allow Ethernet to trigger the buffer baseband, the AGC, and Trigger output 0 (which is mapped to pin 8 on the [wiki:WARPLab/HardwareConfiguration#DebugHeader debug header])
     93{{{
     94nodes(1).wl_triggerManagerCmd('output_config_input_selection',[T_OUT_BASEBAND,T_OUT_AGC,T_OUT_D0],[T_IN_ETH,T_IN_REG]);
     95}}}
     96  '''NOTE:'''  We use both {{{T_IN_ETH}}} and {{{T_IN_REG}}} so this example is compatible with both WARP v2 and WARP v3 hardware.  If using WARP v3 hardware, only {{{T_IN_ETH}}} is needed as the source of the trigger.
     97
     98* For the receive node, if we want to allow the energy detector to trigger the buffer baseband and AGC core:
     99{{{
     100nodes(2).wl_triggerManagerCmd('output_config_input_selection',[T_OUT_BASEBAND,T_OUT_AGC],[T_IN_ENERGY]);
     101}}}
     102  and then setup the configuration of the energy monitoring:
     103{{{
     104rssi_sum_len = 15;
     105
     106nodes(2).wl_triggerManagerCmd('energy_config_average_length',rssi_sum_len);
     107nodes(2).wl_triggerManagerCmd('energy_config_busy_threshold',rssi_sum_len*500);
     108nodes(2).wl_triggerManagerCmd('energy_config_busy_minlength',10);
     109nodes(2).wl_triggerManagerCmd('energy_config_interface_selection',RFA+RFB);
     110}}}
     111
     112* For the receive node, if we connect trigger output 0 (pin 8 of the [wiki:WARPLab/HardwareConfiguration#DebugHeader debug header]) of the transmit node to trigger input 3 (pin 15 of the [wiki:WARPLab/HardwareConfiguration#DebugHeader debug header]) of the receive node, then we can allow trigger input 3 to trigger the buffer baseband and the AGC:
     113{{{
     114nodes(2).wl_triggerManagerCmd('output_config_input_selection',[T_OUT_BASEBAND,T_OUT_AGC],[T_IN_D3]);
     115}}}
     116  We will also enable the debounce circuitry on the trigger input to help with noise on the signal line:
     117{{{
     118nodes(2).wl_triggerManagerCmd('input_config_debounce_mode',[T_IN_D3],'enable');
     119}}}
     120  Since the debounce circuitry is enabled, there will be a delay at the receiver node for its input trigger. To better align the transmitter and receiver, we can artifically delay the transmitters trigger outputs that drive the buffer baseband and the AGC:
     121{{{
     122nodes(1).wl_triggerManagerCmd('output_config_delay',[T_OUT_BASEBAND,T_OUT_AGC],[50]); %50ns delay
     123}}}
     124  '''NOTE:''' The 50 ns delay was measured using the oscilloscope.  The procedure can be found here (Coming soon ...). 
     125
     126* If we want to clear the triggers on the receiver, we can:
     127{{{
     128nodes(2).wl_triggerManagerCmd('output_state_clear',[T_OUT_BASEBAND,T_OUT_AGC]);
     129}}}
     130
     131
     132== Getting Help ==
     133
     134If you have any additional questions, please post to the [http://warp.rice.edu/forums/ WARP Forums].
    16135
    17136
    18137
     138== Tips ==
    19139
    20 == Examples ==
     140Coming soon ...
    21141
    22142
     
    24144
    25145
    26 == Getting Help ==
    27146
    28 
    29 
    30 
    31 
    32 == Tips ==
    33