21 | | || WARP v2 || 6.2 || Jul-2012 || 13.4 || [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_2x2_v06_00_FPGAv2.bit?rev=1755 WARPLab_2x2_v06_00_FPGAv2.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_2x2_v06_00_FPGAv2.ace?rev=1755 WARPLab_2x2_v06_00_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_00_FPGAv2.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv2.zip] || [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_4x4_v06_00_FPGAv2.bit?rev=1755 WARPLab_4x4_v06_00_FPGAv2.bit][[BR]][export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_4x4_v06_00_FPGAv2.ace?rev=1755 WARPLab_4x4_v06_00_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_00_FPGAv2.zip WARPLab_ReferenceDesign_4x4_v06_00_FPGAv2.zip] || |
22 | | || WARP v1 || 6.2 || Jul-2012 || 10.1.03 || [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_2x2_v06_00_FPGAv1.bit?rev=1755 WARPLab_2x2_v06_00_FPGAv1.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_2x2_v06_00_FPGAv1.ace?rev=1755 WARPLab_2x2_v06_00_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_00_FPGAv1.zip WARPLab_ReferenceDesign_2x2_v06_00_FPGAv1.zip] || [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_4x4_v06_00_FPGAv1.bit?rev=1755 WARPLab_4x4_v06_00_FPGAv1.bit][[BR]][export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_4x4_v06_00_FPGAv1.ace?rev=1755 WARPLab_4x4_v06_00_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_00_FPGAv1.zip WARPLab_ReferenceDesign_4x4_v06_00_FPGAv1.zip] || |
| 21 | || WARP v2 || 6.0 || Jul-2012 || 13.4 || [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_2x2_v06_00_FPGAv2.bit WARPLab_2x2_v06_00_FPGAv2.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_2x2_v06_00_FPGAv2.ace?rev=1755 WARPLab_2x2_v06_00_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_00_FPGAv2.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv2.zip] || [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_4x4_v06_00_FPGAv2.bit WARPLab_4x4_v06_00_FPGAv2.bit][[BR]][http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_4x4_v06_00_FPGAv2.ace WARPLab_4x4_v06_00_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_00_FPGAv2.zip WARPLab_ReferenceDesign_4x4_v06_00_FPGAv2.zip] || |
| 22 | || WARP v1 || 6.0 || Jul-2012 || 10.1.03 || [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_2x2_v06_00_FPGAv1.bit WARPLab_2x2_v06_00_FPGAv1.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_2x2_v06_00_FPGAv1.ace?rev=1755 WARPLab_2x2_v06_00_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_00_FPGAv1.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv1.zip] || [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_4x4_v06_00_FPGAv1.bit WARPLab_4x4_v06_00_FPGAv1.bit][[BR]][http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_4x4_v06_00_FPGAv1.ace WARPLab_4x4_v06_00_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_00_FPGAv1.zip WARPLab_ReferenceDesign_4x4_v06_00_FPGAv1.zip] || |