Changes between Version 7 and Version 8 of cores/fmc_bb_4da_bridge


Ignore:
Timestamp:
Feb 18, 2013, 10:53:45 PM (11 years ago)
Author:
murphpo
Comment:

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  • cores/fmc_bb_4da_bridge

    v7 v8  
    1111The fmc_bb_4da_bridge core has inputs which must be connected to internal clock and data signals in the XPS project.
    1212
    13 == Clocks ==
     13=== Clocks ===
    1414
    1515There are two clock inputs which must be connected:
    … …  
    1717 * sys_samp_clk_90: must be a 90-degree phase-shifted version of sys_samp_clk (Virtex-6 MMCMs can generate this)
    1818
    19 == Data ==
     19=== Data ===
    2020There are four data ports, one per DAC output. The labels of these ports match the labels on the FMC-BB-4DA board ("DAC_A", "DAC_B", etc.).
    2121 * user_DAC_A: data for DAC A
    … …  
    2929The ports below must be mapped to top-level outputs in the XPS project, and constrained to the appropriate pins in the project UCF file.
    3030
    31 
    32 '''External Ports:'''
    3331||= Port =||= Direction =||= Width =||= Connection =||
    3432|| DAC_AB_DB || Output ||  12  || DACs A/B AD9116 data port ||
    … …  
    4543|| DAC_CD_PWDN || Output ||  1  || DACs C/D AD9116 Power Down control (tied to 0) ||
    4644
     45== Instantiating the Core ==
     46The MHS and UCF snippets below show how to instantiate the fmc_bb_4da_bridge core in an XPS project for WARP v3.
     47
     48In system.mhs:
     49{{{#!sh
     50#Top-level ports
     51...
     52##FMC-BB-4DA pins
     53# DAC data busses
     54 PORT DAC_AB_DB = DAC_AB_DB, DIR = O, VEC = [0:13]
     55 PORT DAC_CD_DB = DAC_CD_DB, DIR = O, VEC = [0:13]
     56# DAC_AB clock/control
     57 PORT DAC_AB_CLK = DAC_AB_CLK, DIR = O
     58 PORT DAC_AB_PINMD = DAC_AB_PINMD, DIR = O
     59 PORT DAC_AB_PWDN = DAC_AB_PWDN, DIR = O
     60 PORT DAC_AB_CLKMD = DAC_AB_CLKMD, DIR = O
     61 PORT DAC_AB_FORMAT = DAC_AB_FORMAT, DIR = O
     62# DAC_CD clock/control
     63 PORT DAC_CD_CLK = DAC_CD_CLK, DIR = O
     64 PORT DAC_CD_PINMD = DAC_CD_PINMD, DIR = O
     65 PORT DAC_CD_PWDN = DAC_CD_PWDN, DIR = O
     66 PORT DAC_CD_CLKMD = DAC_CD_CLKMD, DIR = O
     67 PORT DAC_CD_FORMAT = DAC_CD_FORMAT, DIR = O
     68
     69...
     70
     71BEGIN fmc_bb_4da_bridge
     72 PARAMETER INSTANCE = fmc_bb_4da_bridge_0
     73 PARAMETER HW_VER = 1.00.b
     74## Widths of user data ports
     75 PARAMETER USER_DAC_A_BITS = 12
     76 PARAMETER USER_DAC_B_BITS = 12
     77 PARAMETER USER_DAC_C_BITS = 12
     78 PARAMETER USER_DAC_D_BITS = 12
     79## Internal clocks
     80 PORT sys_samp_clk = clk_80MHz
     81 PORT sys_samp_clk_90 = clk_80MHz_90degphase
     82## User data ports
     83 PORT user_DAC_A = data_12_bits_for_DAC_A
     84 PORT user_DAC_B = data_12_bits_for_DAC_B
     85 PORT user_DAC_C = data_12_bits_for_DAC_C
     86 PORT user_DAC_D = data_12_bits_for_DAC_D
     87## Data outputs
     88 PORT DAC_AB_DB = DAC_AB_DB
     89 PORT DAC_CD_DB = DAC_CD_DB
     90## Clock outputs
     91 PORT DAC_AB_CLK = DAC_AB_CLK
     92 PORT DAC_CD_CLK = DAC_CD_CLK
     93## Control outputs
     94 PORT DAC_AB_PINMD = DAC_AB_PINMD
     95 PORT DAC_AB_PWDN = DAC_AB_PWDN
     96 PORT DAC_AB_CLKMD = DAC_AB_CLKMD
     97 PORT DAC_AB_FORMAT = DAC_AB_FORMAT
     98 PORT DAC_CD_PINMD = DAC_CD_PINMD
     99 PORT DAC_CD_PWDN = DAC_CD_PWDN
     100 PORT DAC_CD_CLKMD = DAC_CD_CLKMD
     101 PORT DAC_CD_FORMAT = DAC_CD_FORMAT
     102END
     103
     104}}}
     105
     106In system.ucf:
     107{{{#!sh
     108
     109...
     110
     111NET "DAC_AB_CLK" LOC = H20 | IOSTANDARD = LVCMOS25; #FMC_LA09_N
     112NET "DAC_AB_PINMD" LOC = F21 | IOSTANDARD = LVCMOS25; #FMC_LA00_CC_P
     113NET "DAC_AB_PWDN" LOC = B20 | IOSTANDARD = LVCMOS25; #FMC_LA01_CC_P
     114NET "DAC_AB_CLKMD" LOC = G20 | IOSTANDARD = LVCMOS25; #FMC_LA00_CC_N
     115NET "DAC_AB_FORMAT" LOC = E22 | IOSTANDARD = LVCMOS25; #FMC_LA02_P
     116
     117NET "DAC_AB_DB<13>" LOC = F20 | IOSTANDARD = LVCMOS25; #FMC_LA07_N
     118NET "DAC_AB_DB<12>" LOC = A24 | IOSTANDARD = LVCMOS25; #FMC_LA08_N
     119NET "DAC_AB_DB<11>" LOC = F19 | IOSTANDARD = LVCMOS25; #FMC_LA07_P
     120NET "DAC_AB_DB<10>" LOC = E21 | IOSTANDARD = LVCMOS25; #FMC_LA05_N
     121NET "DAC_AB_DB<9>" LOC = A23 | IOSTANDARD = LVCMOS25; #FMC_LA08_P
     122NET "DAC_AB_DB<8>" LOC = G22 | IOSTANDARD = LVCMOS25; #FMC_LA06_N
     123NET "DAC_AB_DB<7>" LOC = D21 | IOSTANDARD = LVCMOS25; #FMC_LA05_P
     124NET "DAC_AB_DB<6>" LOC = D19 | IOSTANDARD = LVCMOS25; #FMC_LA04_N
     125NET "DAC_AB_DB<5>" LOC = G21 | IOSTANDARD = LVCMOS25; #FMC_LA06_P
     126NET "DAC_AB_DB<4>" LOC = E19 | IOSTANDARD = LVCMOS25; #FMC_LA04_P
     127NET "DAC_AB_DB<3>" LOC = C23 | IOSTANDARD = LVCMOS25; #FMC_LA03_N
     128NET "DAC_AB_DB<2>" LOC = B23 | IOSTANDARD = LVCMOS25; #FMC_LA03_P
     129NET "DAC_AB_DB<1>" LOC = C19 | IOSTANDARD = LVCMOS25; #FMC_LA01_CC_N
     130NET "DAC_AB_DB<0>" LOC = E23 | IOSTANDARD = LVCMOS25; #FMC_LA02_N
     131
     132NET "DAC_CD_CLK" LOC = F13 | IOSTANDARD = LVCMOS25; #FMC_LA28_N
     133NET "DAC_AB_PINMD" LOC = D20 | IOSTANDARD = LVCMOS25; #FMC_LA11_N
     134NET "DAC_AB_PWDN" LOC = H13 | IOSTANDARD = LVCMOS25; #FMC_LA16_N
     135NET "DAC_AB_CLKMD" LOC = G12 | IOSTANDARD = LVCMOS25; #FMC_LA16_P
     136NET "DAC_AB_FORMAT" LOC = G13 | IOSTANDARD = LVCMOS25; #FMC_LA15_P
     137
     138NET "DAC_CD_DB<13>" LOC = E13 | IOSTANDARD = LVCMOS25; #FMC_LA28_P
     139NET "DAC_CD_DB<12>" LOC = J10 | IOSTANDARD = LVCMOS25; #FMC_LA29_N
     140NET "DAC_CD_DB<11>" LOC = J11 | IOSTANDARD = LVCMOS25; #FMC_LA29_P
     141NET "DAC_CD_DB<10>" LOC = D11 | IOSTANDARD = LVCMOS25; #FMC_LA24_P
     142NET "DAC_CD_DB<9>" LOC = D12 | IOSTANDARD = LVCMOS25; #FMC_LA25_P
     143NET "DAC_CD_DB<8>" LOC = B13 | IOSTANDARD = LVCMOS25; #FMC_LA21_N
     144NET "DAC_CD_DB<7>" LOC = A11 | IOSTANDARD = LVCMOS25; #FMC_LA26_P
     145NET "DAC_CD_DB<6>" LOC = B12 | IOSTANDARD = LVCMOS25; #FMC_LA21_P
     146NET "DAC_CD_DB<5>" LOC = A14 | IOSTANDARD = LVCMOS25; #FMC_LA22_N
     147NET "DAC_CD_DB<4>" LOC = E14 | IOSTANDARD = LVCMOS25; #FMC_LA19_N
     148NET "DAC_CD_DB<3>" LOC = J12 | IOSTANDARD = LVCMOS25; #FMC_LA20_N
     149NET "DAC_CD_DB<2>" LOC = F14 | IOSTANDARD = LVCMOS25; #FMC_LA19_P
     150NET "DAC_CD_DB<1>" LOC = H12 | IOSTANDARD = LVCMOS25; #FMC_LA20_P
     151NET "DAC_CD_DB<0>" LOC = H14 | IOSTANDARD = LVCMOS25; #FMC_LA15_N
     152
     153...
     154
     155}}}
     156
    47157== Source ==
    48158
    49159The full hardware and software source code is available in the repository: [source:/PlatformSupport/CustomPeripherals/pcores/fmc_bb_4da_bridge_v1_00_b]. The Verilog source code is made available under the [wiki:/license WARP license].
    50