= FMC-BB-4DA Bridge (fmc_bb_4da_bridge) =

The fmc_bb_4da_bridge core implements the output logic for interfacing user designs with the digital interfaces of the AD9116 DACs on the FMC-BB-4DA module. The AD9116 digital ports are double data rate (DDR) interfaces with interleaved I/Q. The fmc_bb_4da_bridge core uses ODDR primitives in the FPGA IOBs to efficiently translate between the external interleaved ports and internal separate busses. One fmc_bb_4da_bridge instance implements the digital interfaces for both AD9116 devices on the FMC-BB-4DA module.

The fmc_bb_4da_bridge core is packaged as a pcore to be instantiated in an XPS project. The design has been tested in hardware using Xilinx ISE 13.4. The fmc_bb_4da_bridge core does not attach to a processor bus, so there is no driver.

The latest revision of the core is v1.00.b, available in the repository: [source:/PlatformSupport/CustomPeripherals/pcores/fmc_bb_4da_bridge_v1_00_b fmc_bb_4da_bridge_v1_00_b].

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== Internal Connections ==
The fmc_bb_4da_bridge core has inputs which must be connected to internal clock and data signals in the XPS project.

== Clocks ==

There are two clock inputs which must be connected:
 * sys_samp_clk: must be synchronous with and valid for registering the user-supplied data signals
 * sys_samp_clk_90: must be a 90-degree phase-shifted version of sys_samp_clk (Virtex-6 MMCMs can generate this)

== Data ==
There are four data ports, one per DAC output. The labels of these ports match the labels on the FMC-BB-4DA board ("DAC_A", "DAC_B", etc.).
 * user_DAC_A: data for DAC A
 * user_DAC_B: data for DAC B
 * user_DAC_C: data for DAC C
 * user_DAC_D: data for DAC D

The width of each port is configurable via an HDL parameter. These parameters are exposed via the "Customize IP Core" GUI in XPS. The width specified in the parameter must match the width of the signal tied to the corresponding port. The width must be <= 16 bits. Up to 12 MSB of the user-supplied signal will be used to drive the DAC's digital input. For user-supplied signals smaller than 12 bits, unused LSB will be driven to 0.

== External Connections ==
The ports below must be mapped to top-level outputs in the XPS project, and constrained to the appropriate pins in the project UCF file.


'''External Ports:'''
||= Port =||= Direction =||= Width =||= Connection =||
|| DAC_AB_DB || Output ||  12  || DACs A/B AD9116 data port ||
|| DAC_AB_CLK || Output ||  1  || DACs A/B AD9116 clock ||
|| DAC_AB_PINMD || Output ||  1  || DACs A/B AD9116 Pin Mode control (tied to 1) ||
|| DAC_AB_CLKMD || Output ||  1  || DACs A/B AD9116 Clock Mode control (tied to 0) ||
|| DAC_AB_FORMAT || Output ||  1  || DACs A/B AD9116 Format control (tied to 1) ||
|| DAC_AB_PWDN || Output ||  1  || DACs A/B AD9116 Power Down control (tied to 0) ||
|| DAC_CD_DB || Output ||  12  || DACs C/D AD9116 data port ||
|| DAC_CD_CLK || Output ||  1  || DACs C/D AD9116 clock ||
|| DAC_CD_PINMD || Output ||  1  || DACs C/D AD9116 Pin Mode control (tied to 1) ||
|| DAC_CD_CLKMD || Output ||  1  || DACs C/D AD9116 Clock Mode control (tied to 0) ||
|| DAC_CD_FORMAT || Output ||  1  || DACs C/D AD9116 Format control (tied to 1) ||
|| DAC_CD_PWDN || Output ||  1  || DACs C/D AD9116 Power Down control (tied to 0) ||

== Source ==

The full hardware and software source code is available in the repository: [source:/PlatformSupport/CustomPeripherals/pcores/fmc_bb_4da_bridge_v1_00_b]. The Verilog source code is made available under the [wiki:/license WARP license].