| 1 | = WARP v3 AD Controller (w3_ad_controller) = |
| 2 | |
| 3 | This core implements an SPI master for reading/writing registers in the AD9963 analog converters on the WARP v3 board. |
| 4 | |
| 5 | The w3_ad_controller core is packaged as a pcore which can instantiated in an XPS project. The design has been tested in hardware using Xilinx ISE 13.4. |
| 6 | |
| 7 | == Hardware == |
| 8 | |
| 9 | The MHS snippet below shows the w3_ad_controller instantiation used in the WARP v3 reference projects. The memory address is intentionally invalid; you must run "Generate Addresses" after adding the core. |
| 10 | |
| 11 | {{{ |
| 12 | #!sh |
| 13 | |
| 14 | #Top level ports |
| 15 | ... |
| 16 | # AD9963 ADC/DAC control pins (RFA & RFB) |
| 17 | PORT RFA_AD_spi_cs_n_pin = RFA_AD_spi_cs_n, DIR = O |
| 18 | PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio, DIR = IO |
| 19 | PORT RFA_AD_spi_sclk_pin = RFA_AD_spi_sclk, DIR = O |
| 20 | PORT RFA_AD_reset_n_pin = RFA_AD_reset_n, DIR = O |
| 21 | PORT RFB_AD_spi_cs_n_pin = RFB_AD_spi_cs_n, DIR = O |
| 22 | PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio, DIR = IO |
| 23 | PORT RFB_AD_spi_sclk_pin = RFB_AD_spi_sclk, DIR = O |
| 24 | PORT RFB_AD_reset_n_pin = RFB_AD_reset_n, DIR = O |
| 25 | ... |
| 26 | BEGIN w3_ad_controller |
| 27 | PARAMETER INSTANCE = w3_ad_controller_0 |
| 28 | PARAMETER HW_VER = 3.00.b |
| 29 | PARAMETER C_BASEADDR = 0xFFFFFFFF |
| 30 | PARAMETER C_HIGHADDR = 0x00000000 |
| 31 | BUS_INTERFACE SPLB = plb_primary |
| 32 | PORT RFA_AD_spi_cs_n = RFA_AD_spi_cs_n |
| 33 | PORT RFB_AD_reset_n = RFB_AD_reset_n |
| 34 | PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio |
| 35 | PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio |
| 36 | PORT RFA_AD_spi_sclk = RFA_AD_spi_sclk |
| 37 | PORT RFA_AD_reset_n = RFA_AD_reset_n |
| 38 | PORT RFB_AD_spi_sclk = RFB_AD_spi_sclk |
| 39 | PORT RFB_AD_spi_cs_n = RFB_AD_spi_cs_n |
| 40 | END |
| 41 | ... |
| 42 | }}} |
| 43 | |
| 44 | == Driver == |
| 45 | |
| 46 | The w3_ad_controller pcore includes a C driver to facilitate control of the AD9963s from user code. Refer to the [//svn/WARP/PlatformSupport/CustomPeripherals/pcores/w3_ad_controller_v3_00_b/doc/html/api/index.html w3_ad_controller driver documentation] for more details. |
| 47 | |
| 48 | All driver functions require the base memory address of the w3_iic_eeprom pcore. This address is set in your XPS project. The EDK tools copy this address into a macro in the {{{xparameters.h}}} file when you generate a BSP. The auto-generated macro should be named {{{XPAR_W3_AD_CONTROLLER_0_BASEADDR}}} (assuming your pcore instance is named {{{w3_ad_controller_0}}}, as in the example above). |
| 49 | |
| 50 | {{{ |
| 51 | #!C |
| 52 | //Define our own macro, in case EDK changes its naming scheme in the future |
| 53 | // Assumes pcore instance is named w3_ad_controller_0; confirm in xparameters.h |
| 54 | #define AD_BASEADDR XPAR_W3_AD_CONTROLLER_0_BASEADDR |
| 55 | |
| 56 | }}} |
| 57 | |
| 58 | |
| 59 | == Source == |
| 60 | |
| 61 | The full hardware and software source code is available in the repository: [source:/PlatformSupport/CustomPeripherals/pcores/w3_ad_controller_v3_00_b]. The VHDL, Verilog and C source code are made available under the [wiki:/license WARP license]. |