| 37 | 37 | The w3_clock_controller driver provides functions to configure the AD9512 output dividers, thereby configuring the frequency of the clocks feeding the RF interface AD9963 chips (the ADC/DAC chips). It is critical that the AD9512->AD9963 clock frequency be consistent with all other rates in the FPGA->DAC and ADC->FPGA interfaces. The combination of AD9963 clock settings (DLL state, ADC/DAC clock source, etc.), AD9963 filter settings (interpolation/decimation rates), AD9512 dividers and internal FPGA->w3_ad_bridge clock connections must all agree. Refer to the [wiki:HardwareUsersGuides/WARPv3/RF WARP v3 User Guide RF section] for more details and examples of valid AD9512/AD9963/FPGA configurations. |
