Changes between Version 1 and Version 2 of cores/w3_iic_eeprom
- Timestamp:
- Aug 11, 2012, 9:39:22 PM (12 years ago)
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cores/w3_iic_eeprom
v1 v2 3 3 This core implements an IIC master for accessing the IIC EEPROM on the WARP v3 board. The core provides a PLBv46 slave interface for control from user code. 4 4 5 The w3_iic_eeprom core is packaged as a pcore which can instantiated in an XPS project. The design has been tested in hardware using Xilinx ISE 13.4. 6 5 7 == Hardware == 6 8 7 The w3_iic_eeprom core is packaged as a pcore which can instantiated in an XPS project. The HDL has been tested in hardware using ISE / XPS 13.4.9 The MHS snippet below shows the w3_iic_eeprom instantiation used in the WARP v3 reference projects. The memory address is intentionally invalid; you must run "Generate Addresses" after adding the core. 8 10 9 The MHS snippet below shows the w3_iic_eeprom instantiation used in the WARP v3 reference projects.Note that the top-level port name and internal net names are identical. This is a requirement imposed by XPS for connecting the tri-state IIC signals.11 Note that the top-level port name and internal net names are identical. This is a requirement imposed by XPS for connecting the tri-state IIC signals. 10 12 11 13 {{{ … … 21 23 PARAMETER INSTANCE = w3_iic_eeprom_0 22 24 PARAMETER HW_VER = 1.00.b 23 PARAMETER C_BASEADDR = 0x cbe0000024 PARAMETER C_HIGHADDR = 0x cbe0ffff25 PARAMETER C_BASEADDR = 0xFFFFFFFF 26 PARAMETER C_HIGHADDR = 0x00000000 25 27 BUS_INTERFACE SPLB = plb_primary 26 28 PORT iic_scl = IIC_EEPROM_iic_scl_pin … … 32 34 == Driver == 33 35 34 The w3_iic_eeprom pcore includes a driver to facilitate accessing the EEPROM from user code. A simple example of using the driver is given below. Refer to the [export:/PlatformSupport/CustomPeripherals/pcores/w3_iic_eeprom_v1_00_b/doc/html/api/index.html w3_iic_eeprom driver documentation] for more details.36 The w3_iic_eeprom pcore includes a C driver to facilitate accessing the EEPROM from user code. A simple example of using the driver is given below. Refer to the [//svn/WARP/PlatformSupport/CustomPeripherals/pcores/w3_iic_eeprom_v1_00_b/doc/html/api/index.html w3_iic_eeprom driver documentation] for more details. 35 37 36 38 All driver functions require the base memory address of the w3_iic_eeprom pcore. This address is set in your XPS project. The EDK tools copy this address into a macro in the {{{xparameters.h}}} file when you generate a BSP. The auto-generated macro should be named {{{XPAR_W3_IIC_EEPROM_0_BASEADDR}}} (assuming your pcore instance is named {{{w3_iic_eeprom_0}}}, as in the example above). … … 64 66 == Source == 65 67 68 The full hardware and software source code is available in the repository: [source:/PlatformSupport/CustomPeripherals/pcores/w3_iic_eeprom_v1_00_b]. The VHDL, Verilog and C source code are made available under the [wiki:/license WARP license]. 69 70 The HDL for w3_iic_eeprom incorporates the excellent [http://opencores.org/project,i2c OpenCores I2C controller core]. The unmodified code for the version of the OpenCores code used in this core is included in the [source:/PlatformSupport/CustomPeripherals/pcores/w3_iic_eeprom_v1_00_b/opencores_src opencores_src] subdirectory of the w3_iic_eeprom pcore. Refer to the comments in [source:/PlatformSupport/CustomPeripherals/pcores/w3_iic_eeprom_v1_00_b/opencores_src/rtl/verilog/i2c_master_top.v i2c_master_top.v] for the author's copyright and warranty notice.
