Changes between Initial Version and Version 1 of howto/XPS_Address_Assignment


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Timestamp:
Nov 11, 2013, 3:55:52 PM (9 years ago)
Author:
welsh
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  • howto/XPS_Address_Assignment

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     1= Assigning Addresses for Peripherals in XPS for WARPLab =
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     3Due to changes within the WARPLab Architecture to improve performance, XPS is no longer able to generate addresses for peripherals automatically.  This is primarily due to the added complexity within the interconnect to improve bandwidth while still meeting the timing constraints.  Therefore, it has become necessary to be able to manually assign addresses to peripherals.  This tutorial will help understand addressing within WARPLab and allow you to add custom peripherals into the WARPLab Reference design. 
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     5NOTE:  This tutorial is based on [wiki:WARPLab/Downloads WARPLab 7.3.0] but the concepts should apply generically.
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     7== Understanding the FPGA Architecture ==
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     9The first key to being able to manually assign addresses to peripherals is to have an understanding of the [wiki:WARPLab/FPGAArchitecture FPGA Architecture].  If we look at the [wiki:WARPLab/FPGAArchitecture/WARPLAB_7_3_0 WARPLab 7.3.0 Architecture], we can see that there are 4 interconects:  AXI 0, AXI 1, AXI Lite 0 and AXI Lite 1.  Depending on where you connect your peripheral, this will determine what Masters have access to the peripheral as well as what address range to use for your peripheral. 
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     11=== Microblaze Configuration ===
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     13To start, we need to first understand the address ranges of each interconnect.  This starts with the configuration of the Microblaze processor:
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     15[[Image(Microblaze_Configuration.png, 600px)]]
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     17The Microblaze processor supports a 32 bit address space.  For WARPLab 7.3.0, we have divided the address space in half between the cache buses (ie M_AXI_DC and M_AXI_IC) and the peripheral buses (ie M_AXI_DP and M_AXI_IP).  Unfortunately, the size of many address spaces, such as the caches, DDR, etc., must be aligned to powers of 2 in order to reduce address decode complexity.  Therefore, if we want to use both the peripheral and cache buses, the largest address size aligned to a power of 2 that is less than 4GB is 2GB.  Hence, any peripheral accessed via the M_AXI_DC bus must have an address greater than 0x8000_0000 while any peripheral accessed via the M_AXI_DP bus must have an address less than 0x8000_0000. 
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     19=== AXI Interconnect Configuration ===
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     21The next thing to understand are the address ranges of the AXI / AXI interconnects.  To do this, it is necessary to look at the axi2axi_connector peripherals within the WARPLab design.  There are two axi2axi_connector peripherals in the WARPLab 7.3.0 reference design which have the following configurations:
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     23==== AXI2AXI Connector 0 ====
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     25[[Image(axi2axi_connector_0.png, 600px)]]
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     27==== AXI2AXI Connector 1 ====
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     29[[Image(axi2axi_connector_1.png, 600px)]]
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     31These connectors define the range of addresses that are passed to the secondary interconnect.  If the address is not decoded by the connector then it is available in the original interconnect attached to the M_AXI_DC or M_AXI_DP buses.  Therefore, if we look at the WARPLab 7.3.0 reference design, we have the following configuration:
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     33||= '''IP Instance''' =||= '''Base Address''' =||= '''High Address''' =||= '''Size''' =||
     34|| AXI Lite 0 || 0x0000_0000 || 0x3FFF_FFFF || 1GB ||
     35|| AXI Lite 1 || 0x4000_0000 || 0x4FFF_FFFF || 256M ||
     36|| AXI Lite 0 || 0x5000_0000 || 0x7FFF_FFFF || 768M ||
     37|| AXI 0 || 0x8000_0000 || 0x80FF_FFFF || 16M ||
     38|| AXI 1 || 0x8100_0000 || 0x81FF_FFFF || 16M ||
     39|| AXI 0 || 0x8200_0000 || 0xFFFF_FFFF || 2G - 32M ||
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     41Therefore, depending on where you connect your peripheral, you will need to use an address in one of the following ranges.
     42
     43== Modifying Addresses in XPS ==
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     45When you open the WARPLab 7.3.0 reference design in XPS, you should see the following:
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     47[[Image(xps_bus_interfaces.png, 600px)]]
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     49This provides a high level view of the bus connections of the peripherals in the WARPLab reference design.  As you can see, each of the AXI interconnect buses are shown in the columns on the left and the connection to the slave port of a peripheral is shown by a dot.  For example, the W3_USERIO peripheral is connected to the axi4lite_0 bus. 
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     51When you add your peripheral to the WARPLab reference design, you need to determine which interconnect you are going to attach it to.  Please note that AXI interconnects cannot have more than 16 slaves.  Also, the more peripherals on an interconnect, the more logic it takes to decode and route transactions which can lead to timing problems if the design is too aggressive. 
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     53Once you have connected your peripheral to an interconnect, you then need to select the "Addresses" tab:
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     55[[Image(xps_addresses_highlight.png, 600px)]]
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     57If you select the "Base Address" of your peripheral, then you can enter the hexadecimal base address of your peripheral on a power of 2 boundary.  The "High Address" will automatically be modified based on the address size of your peripheral.  You just need to make sure that you choose an appropriate address based on where your peripheral is connected. 
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     59For example, if your peripheral is connected to AXI Lite 1, then you should make sure that the number you enter for the "Base Address" is between 0x4000_0000 and 0x4FFF_FFFF. 
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     61If you have any questions, please use the [http://warpproject.org/forums/ forums].
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