WARP Project Forums - Wireless Open-Access Research Platform

Hi Murphpo,

Are there two on-board oscillators? One has a output of 20MHz, and the other has a output of 40MHz.
To fully synchronized the boards, do you suggest feed RF reference clock and sampling clock from the same clock source?
Thx.

Rui

murphpo wrote:

Either waveform is fine. You'll achieve lower jitter with the fast slew of a square wave. To fully synchronize nodes you must supply both the RF reference clock and sampling clock. The RF ref must be 20MHz (same as the on-board oscillator) or 40MHz (requires minor change to radio_controller code). The sampling clock can be any value supported by the ADCs/DACs and by your FPGA design. The on-board oscillator is 40MHz, the value assumed by all the WARP reference designs.

Hi Murphpo,

We plan to use GPS disciplined oscillators (GPSDO) to achieve clock sync across distributive boards. But the GPSDOs we have found so far only provide 10MHz reference clock. I guess we need to add X4 frequency multipliers to get 40MHz output and feed it to both the sampling reference clock and radio RF reference clock on the board.

But we are afraid that frequency multipliers may kill the clock synchronization across distributive clock sources, as we do not have too many experiences dealing with clocks and frequency multipliers. Do you happen to know if someone else has done similar designs before?
Thx.

Rui

murphpo wrote:

Are there two on-board oscillators? One has a output of 20MHz, and the other has a output of 40MHz.

Yes. This is explained in the Clock Board User Guide.

To fully synchronized the boards, do you suggest feed RF reference clock and sampling clock from the same clock source?

This is certainly an option. You can also use different clocks if your application requires a sampling frequency that isn't a multiple of 40MHz.

Hi Murphpo,

From the datasheet of the GPS disciplined oscillator, it says the frequency stability over temperature is (+-6E-9), and the frequency stability over 24hrs (<1E-12), when the oscillator is locked to the GPS signal.
Its measured ADEV 1s<7E-12 (25 degree, no motion/airflow)
Feel free to give some comments.

Rui

murphpo wrote:

I'm not aware of anyone who has used that setup. It seems like it should work. What are the jitter characteristics of the 10MHz clock output?

Since I want to feed both sampling clock and RF reference clock from the same external reference clock, but my external clock unit only has one output port, can I just feed J2 on WARP clock board with my 40MHz external ref clock, and then connect J4 with J3? If I understand the setup correctly, J4 outputs an identical signal to that of J2

That should work. We've seen other users do this successfully.

You will need to modify the radio_controller driver to configure the MAX2829 for a 40MHz reference clock. The code for this is already in the driver but is commented out by default. See radio_controller_basic.c.

Nope- the PLL tuning words don't change with a 40MHz reference frequency, only the reference divider (the value affected by the radio_controller driver change).

Just to clarify, you want (Ext 40MHz -> J2 -> RF ref clock buffer -> J4 -> J3 -> Sampling clock buffer)?

If so, this is possible. You would need to configure the Clock Board to select J2 and J3 as the clock sources (i.e. both RF ref and sampling clocks external) and enable the J4 output. You would also need to make a physical connection from J4 -> J3 using a short coax cable.

Hi  Murphpo,

Can you be more specific on how to configure the clock board to select J2 and J3 as the clock sources, and how to activate the J4 output? Do they need a change of the hardware/software codes?
I have seen your reply in another thread that the first one just requires the setting of two switches on Radio Board on slot 2.
Thanks a lot.

Rui

murphpo wrote:

Just to clarify, you want (Ext 40MHz -> J2 -> RF ref clock buffer -> J4 -> J3 -> Sampling clock buffer)?

If so, this is possible. You would need to configure the Clock Board to select J2 and J3 as the clock sources (i.e. both RF ref and sampling clocks external) and enable the J4 output. You would also need to make a physical connection from J4 -> J3 using a short coax cable.

Hi Murphpo,

For the top two switches on radio board in slot 2 for WARP v2.2, do you mean switch 4 and 3 of that dip switch??
Thanks.

Rui

murphpo wrote:

Recent WARPLab reference designs use the top two positions of the DIP switch on the Radio Board in slot 2 to configure the source of the RF and sampling clocks. Assert the switch to select the off-board clock source. For the configuration you describe above you want both clocks configured for off-board sources. I don't recall if the clock forwarding ports (J2) are enabled by default. If not you need to enable them via the GUI for the clk_board_config core in XPS (double click the core in System Assembly View, enable the outputs you want, click OK, then re-built hardware).

Hmm That is weird.
Later last night I used our spare board for the test. It is actually switch 1 and 2 of that dip switchthat give me the selection of off-board clock input. I tried switch 3 and 4, the radio reference clock output port still gave me 20MHz instead of 40MHz (our external clock).
Thanks.

Rui

murphpo wrote:

For the top two switches on radio board in slot 2 for WARP v2.2, do you mean switch 4 and 3 of that dip switch??

Yes.