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Hi,
I am working on warp V2 & warp V3.
In warp V2 I was successfully able to perform most of the M-file examples ( By modifying to single board, ie siso) by using the Bitstream WARPLab_2x2_v05_02_FPGAv2.bit, but when i tried with different bitstreams ie for V6p2 & V6p3, i was unable to execute any of the M-files as i am getting the following errors for one of the workshop M-files
No ACK received - Connection has timed out.
No ACK received - Connection has timed out.
No ACK received - Connection has timed out.
??? Operation terminated by user during ==> warplab_pktSend at 12
In ==> warplab_setRadioParameter at 8
datarec = warplab_pktSend(nodeHandle, pktDataTx);
In ==> warplab_SpectrumSensing_WorkshopExercise_Instructors_ContTx at 49
warplab_setRadioParameter(udp_node1,CARRIER_CHANNEL,Node1_CarrierChannel);
I was able to execute the same M-file in V05 bitstream. When ever i program warp V2 with V6p2 & V6p3( downloaded bitstream from website), I am unable to ping to 10.0.0.1, but i was able to ping with v5_02.bit, but i fpga get successfully configured ( verified from serial port & 7 segment)
I am facing similar issue with warp V3, i.e not able ping whenever i configure warpLab bitstreams ie both V6.3b & v6.2, I am unable to ping hence cant run any M-files. Do we have to configure ethernet port for 1Gbps for warp v3 boards?
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faizan wrote:
Do we have to configure ethernet port for 1Gbps for warp v3 boards?
You are exactly right, and I suspect this is the problem you are seeing. In the jump to WARPLab v6 and beyond, we made the default Ethernet speed be 1Gbps for WARP v2 and WARP v3. This is not only because of the speed up in performance, but because old 100Mbps Ethernet switches are increasingly difficult to find. If you are using a 100Mbps switch with your WARPLab set up, then that won't work with the default bitstreams.
If you don't have access to a gigabit switch, it's just a one-line C-code change to modify operating speed of WARPLab back down to 100Mbps. This will work on either WARP v2 or WARP v3.
The one line of code that needs to change is a call to the TEMAC that sets its operating speed:
XLlTemac_SetOperatingSpeed(&TemacInstance, ENET_LINK_SPEED);
In the WARPLab reference design, the #define of ENET_LINK_SPEED is on Line 96 of warplab.c.
I bet that making that change and rebuilding the bitstream or changing your Ethernet switch will fix the problems are are observing.
Also, don't forget to update your Matlab path to the newest M-code reference files (v6.3). The older v5_02 reference M-code won't work with WARPLab v6 and beyond. We changed the IP address of the sync packets from *.244 to *.255 since it is effectively broadcast traffic.
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Thanks for the reply.
how about OFDMref Design ie NOMAC & CSMA? Is the Ethernet configured for Gigabit Switch? How can i change that 100Mbps?
Kindly Oblige.
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Yes, all reference designs for WARP v3 assume a 1Gb Ethernet connection. The same XLlTemac call will set the MAC-PHY speed in the OFDM ref design as well.
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Hi,
Thanks for the reply
chrishunter wrote:
If you don't have access to a gigabit switch, it's just a one-line C-code change to modify operating speed of WARPLab back down to 100Mbps. This will work on either WARP v2 or WARP v3.
As per discussed in above post i have changed the C-code for 100mbps, i was able to ping ( warp lab) to both the warp V3 boards with 100Mbps switch.
I am facing issue when i run a M-code from M_code_examples ie it's given error:
??? Index exceeds matrix dimensions.
Error in ==> warplab_readSMRO at 18
rawData = rawData(1:numSamples);
Error in ==> warplab_mimo_2x2_example_TxRx_v3 at 264
[Node2_Radio1_RawRxData] = warplab_readSMRO(udp_node2, RADIO1_RXDATA, TxLength+TxDelay);
I have referred to few post in the forums & i have tried " arp -s 10.0.0.244 ff-ff-ff-ff-ff-ff 10.0.0.200", but after running this there's no chnage in the result, as i am getting the same error.
Kindly Oblige.
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You are right about what you read in other forum posts; I'm pretty sure that the sync packet is being dropped. In WARPLab version 6.0 and higher, we moved the IP address of the sync packet from 10.0.0.244 to 10.0.0.255. So, if you are using one of these versions of WARPLab, try this command:
arp -s 10.0.0.255 ff-ff-ff-ff-ff-ff 10.0.0.200
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Thanks for the reply.
We want to communicate between WARP V3 & Warp V2. We were successfully able to do so in WARPLab, by changing few parameters in M-file.
We are unable to communicate in OFDM design, ie in Mac layer, as we are unable to transmit/ receive Dummy packets in NoMac. I am using OFDM desin V 18.1 for V3 & OFDM desin V 16 for V2.
Kindly suggest how can we able achieve this. Kindly suggest the changes in OFDM design so that we can achieve it.
Kindly oblige
Last edited by faizan (2013-Jan-13 02:14:57)
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OFDM ref design v18.1 on WARP v3 will inter-operate with OFDM ref design v18.0 on WARP v2. Ensure both nodes are tuned to the same channel (I don't recall whether nomac.c uses the same default channel in both designs).
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Hi,
chrishunter wrote:
If you don't have access to a gigabit switch, it's just a one-line C-code change to modify operating speed of WARPLab back down to 100Mbps. This will work on either WARP v2 or WARP v3.
How do i downgrade the Ethernet Speed ie from 1Gbps to 100Mbps in WAPLAB 7. I am currently using w3_WARPLab_EDK_2RF_v7.1.0 reference design.
Kindly oblige
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You can make that change on Line 48 of wl_transport.h.
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If you're just getting started, we recommend using the latest WARPLab ref design (currently 7.2).
For WARPLab 7.1 (svn rev 2035) the equivalent #define is ENET_LINK_SPEED.
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The one line of code that needs to change is a call to the TEMAC that sets its operating speed:
Code:
XLlTemac_SetOperatingSpeed(&TemacInstance, ENET_LINK_SPEED);
In the WARPLab reference design, the #define of ENET_LINK_SPEED is on Line 96 of warplab.c.
How can I download bitstream source code to make this change and recompile to get new .bit file???
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How can I download bitstream source code to make this change and recompile to get new .bit file???
The WARPLab Reference Design archive contains the SDK workspace for the software project. To modify the software project you must use the Xilinx SDK to open the project, make your changes, compile the updated software and update the FPGA configuration bitstream. If you're not already familiar with the SDK flow, I suggest working through our getting started tutorials, which introduce the entire tool flow.
Also, please do not post the same question to multiple threads and then email the same the question to us directly. We do our best to answer questions as quickly as possible; asking multiple times does not speed this up.
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Thank you and sorry for that.
The source code on ResearchApps/PHY/WARPLAB/WARPLab7 has a bunch of stuff.
However I am only interested in the files with .bit extension.
Are you knowing which way can I identify those files?
There is C_Code_Reference, M_Code_Reference, M_Code_Examples, XPS_Reference, Sysgen_Reference.
Also can the changes be done in Xilinx Webpack edition?
Thanks,
Last edited by krupeshved (2014-Oct-05 15:32:38)
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There are no bit files in the repository. We provide the source files in the repository for you to create your own bit files.
It seems like you are trying to jump ahead in the process without really understanding what is going on. If you just work through the tutorials and read the on-line documentation, this will give you some good experience with all of the things we are talking about. The main toolchain you need to update software and create new bit files is the Xilinx 14.4 SDK.
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Hello Admin,
I got webpack edition 14.4 and have the Project Navigator running. How to get SDK started on it? Also I read SDK is similar to Eclipse. In that case, there should be a standard library file/project of the BITSTREAMS comprising of different files. I see that http://warpproject.org/trac/browser/Res … B/WARPLab7
has parts of the file but to compile would I need all as one opened in SDK?
Sorry am struggling here, help would be greatly appreciated !!
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Instead of going through Project Navigator, you should just start the SDK directly. I'm not sure the install paths for the webpack edition, but you can find SDK within the full install at:
Start --> All Programs --> Xilinx Design Tools --> ISE Design Suite 14.4 --> EDK --> Xilinx Software Development Kit
or you can just search your computer for the SDK:
Start --> Search programs and files --> Enter: "Xilinx Software" and Windows should be able to find the SDK.
Once you start using the SDK, please use the Introduction to the Xilinx Software Development Kit (SDK) tutorial to get started.
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Thank you Welsh. I see the change is needed in wl_transport.h. Which other files are needed to create the bit stream? Can I open the bit streams downloaded from http://warpproject.org/trac/wiki/WARPLab/QuickStart in Xilix, change it and recompile new bit streams?
Thank you once again.
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Sorry I am confused. I see http://warpproject.org/trac/wiki/WARPLa … ignArchive has all the source code. But there is no option to download all source code as one and opening it in Xilinx SDK. Later I can use those files to generate .bit file.
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To edit the software project you must create an SDK workspace in the SDK_Workspace folder of the reference design archive, then import the reference design SDK projects into your workspace. This is the same process as described in the Intro to SDK exercise Erik linked to above.
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Thank you Admin. I created myworkspace in SSDK_Workspace, imported the 3 projects called w2WarpLab_v7_2rf, w2_WARPLAB WARPLabbsp0 ans w2_warplab_v7_2rf_EDK_v7.4.0_hw_plaftform.
Now after making changes it has created a .metadata file which has .plugin and .lock file. How can I get bitstreams from this?
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