WARP Project Forums - Wireless Open-Access Research Platform

Which reference design are you modifying? If it's the 802.11 design, which CPU should be able to access the new peripheral?

Also, just in case you're using the FMC-RF-2X245 module, you can use the SPI master in the w3_ad_controller core to configure the AD9963 chips. If you're using a third-party FMC module with SPI slave devices, using the Xilinx axi_spi is a good approach.

If you look at the FPGA Architecture (the link is to v1.3.0 b/c we have not generated a diagram for v.1.2.0, but they are similar enough), you can see that each processor has their M_AXI_DP connected to a separate interconnect (i.e. the "MB * Peripheral Bus" interconnect in the picture) and the M_AXI_DC port connected to a shared interconnect (i.e. the "MB Shared" interconnect in the picture).  If you look at how the Microblaze processors are configured, all bus accesses with addresses from 0x0000_0000 to 0x7FFF_FFFF are issued out of the M_AXI_DP port (or to the attached LMB BRAM), while all bus accesses with addresses from 0x8000_0000 to 0xFFFF_FFFF are issued out of the M_AXI_DC port.  So where you connect the new SPI peripheral to the interconnect determines what the valid address range can be.  If you placed the SPI module on the "MB Low Peripheral Bus", then the address must be less than 0x7FFF_FFFF.  This is why an address of 0x5000_0000~0x5000_FFFF will work but an  address of 0xBF58_0000~0xBF58_FFFF does not.  If the peripheral should be shared between CPU High and CPU Low, then you should put in on the "MB Shared" bus and assign an appropriate address.  Otherwise, you should keep it on the "MB Low Peripheral Bus" and use an address less than or equal to 0x7FFF_0000~0x7FFF_FFFF.