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I tried to export a simple DDS design as an EDK pcore with AXI4 interface. I got an error report as the following. I don't recall that we needed to have an explicit "system clock port" for PLB interferes. Do we need something like this now?
--------------------------------- Version Log ----------------------------------
Version Path
System Generator 14.4 C:/Xilinx/14.4/ISE_DS/ISE/sysgen
Matlab 7.13.0.564 (R2011b) C:/MATLAB/R2011b
ISE C:/Xilinx/14.4/ISE_DS/ISE
--------------------------------------------------------------------------------
Summary of Errors:
Error 0001: caught standard exception
Block: Unspecified
--------------------------------------------------------------------------------
Error 0001:
Reported by:
Unspecified
Details:
standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.NetlistInternal: expected system clock
port from the design
--------------------------------------------------------------------------------
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Well, I am not exactly sure I found the reason, but this might have something to do with the 'DDS compiler 5.0' inside the model. I needed to insert an 'add' block between a 'From Register' and the programmable phase input of the 'DDS compiler 5.0' block. With the 'add' block, everything is fine.
I tried to use a 'delay' block instead, but it didn't help. This is very interesting -- 'add' works but not a 'delay' block.
Last edited by zrcao (2016-Jul-15 19:00:53)
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I've never seen that error, glad you found a work around. Does placing a Register block (not Delay) between the From Register and DDS input work too? I usually stick at least 1 Register block between From/To registers and the rest of the core. This helps timing a lot - the From/To registers are tied to the processor's interconnect. With many cores / registers the interconnect signals are commonly among the design's critical paths.
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