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I am currently trying to modify the WARPLAB firmware (C code) to implement a simple CSMA/CA mechanism. This requires real-time RSSI samples every 9 us in the middle of reception. However, it turns out RSSI values in the RSSI buffer will not be updated util the reception is completed. In specific, the rssi values in wl_rssi_buff_a are stale util the reception is finished.
Is there anyway in the WARPLAB firmware I can read the real-time instantaneous RSSI value from the RF radio?
btw, I also try trigger the RX every 9us with rx_length = 360 (9us). But it terms out the time gaps for enabling RX is as large as 70us.
THX
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The ADC which digitizes the RSSI signal runs continuously at 10MSps. The WARPLab Reference Design connects this 10-bit digital RSSI signal to 3 cores in the WARPLab reference design - the AGC, Buffers, and Trigger Processor (follow the warplab_rfa_rssi signal in system.mhs).
None of these cores implements a software-accessible register with the raw RSSI value. You will need to modify the hardware design if you need this functionality. I would suggest modifying the Trigger Processor core (warplab_trigger_proc source) to create a new trigger source based on your CSMA logic.
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Hi murphpo,
I see. Thanks so much for the reply.
I am currently planning to expose the RSSI value by implementing a software-accessible register with the raw RSSI value and put the csma logic into C.
However, I am completely new to FPGA. Could you suggest any example (of adding a register with external input) that I can follow?
Thanks again!
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Our getting started tutorials for WARP v3 are a good resource for this.
The basic steps would be:
-Modify one of the System Generator cores
-Add a new From (software-read-only) register
-Update EDK Processor block
-Increment pcore version number
-Export new pcore
-Update XPS project
-Update HW_VER for pcore to new version
-Rebuild hardware design (Generate Bitstream)
-Export new hardware to SDK
-Update C code
-Add your new C code that implements some functionality around the new register
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