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The ADC for RSSI is 10-bits, but what is the input range designed in WARP radio? The analog RSSI output, according to 2829 data sheets, is [0.5, 2.5]V. So how is the mapping relationship between the analog input value with the digital output value?
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The RSSI ADC is configured for the same voltage range as the RSSI output. This maps 0.5v to digital 0 and 2.5v to digital 1023. In practice, the noise floor of the RSSI signal seems to hover around a digital value of 100. We'll soon be posting some characterization data for our packet detector core which includes plots of real RSSI signals for received OFDM packets.
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(Prob. A)
From the port connection of OFDM referece design V2, I noticed the following two net names:
Net name: "radio_bridge_slot_2_controller_RSSI_ADC_D_radio_controller_0_radio2_RSSI_ADC_D" is used to connect radio_bridge_slot_2 RSSI with radio_controller_0
Net name: "radio_bridge_slot_2_user_RSSI_ADC_D" is used to connect radio_bridge_slot_2 RSSI with both AGC pcore and PKT detector pcore.
Are these two actually the same net? Is it possible to replace AGC and PKT detector pcores while keep using Rice's radio_controller_0 and radio_bridge_x?
(Prob. B)
Can you actually read the current LNA and VGA gain settings in radio_controller_0? In radio_controller.h, there are two functions, WarpRadio_RxLNAGainControl and WarpRadio_RxVGAGainControl, for setting these gains. But I didn't find functions to read the gains.
(Prob. C)
How do you control the Rx gain from radio_controller_0? I didn't find any output port of radio_controller_0 that is connected to the User_RFRx_gain port or the User_RFBB_gain port of radio_bridge_x. You can just check the data with, there is not 7 bits data, or one port with 5 bits and another with 2 bits that are intended for rx power control.
Last edited by zrcao (2007-May-01 15:10:52)
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The radio bridge core is designed so that users never have to connect/modify ports on the controller. Ports that users need are all provided on the radio bridge, named user_<portName>. If you look at the radio bridge source code, you'll see that the user ports are just registered versions of the top-level IO. This stage of registers helps with timing by packing the registers into the IOBs and fanning out from there.
A) The bridge has one input for RSSI_ADC_D (port radio_RSSI_ADC_D) and two outputs (ports controller_RSSI_ADC_D and user_RSSI_ADC_D). The outputs are identical, both registered copies of the radio_RSSI_ADC_D input. We provide two ports so that one can be automatically connected to the radio_controller when using Base System Builder while the other is open for user applications.
B) You cannot read values from the radio. If you're using software gain control, you need to keep track of gain settings in your code. If you're using AGC (i.e. hardware gain control), you can monitor the two user gain signals (ports User_RxBB_gain and User_RxRF_gain) on the radio bridge. These signals will then be driven by the AGC core into both the radio bridge (for output to the radio itself) and your core for monitoring. We do this for multiple-antenna switching diversity receivers.
C) The radio controller can only control gains via software (via the radio's SPI interface). You have to provide a custom core (or use our AGC) which drivers the user gain ports if you want hardware-level control of gains.
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