1 | # ##############################################################################
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2 | # Created by Base System Builder Wizard for Xilinx EDK 8.2.01 Build EDK_Im_Sp1.3
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3 | # Wed Jan 24 09:12:18 2007
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4 | # Target Board: Rice University - WARP Project WARP FPGA and Radio Boards Rev FPGA 1.2 & Radio 1.4
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5 | # Family: virtex2p
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6 | # Device: XC2VP70
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7 | # Package: FF1517
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8 | # Speed Grade: -6
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9 | # Processor: PPC 405
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10 | # Processor clock frequency: 200.000000 MHz
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11 | # Bus clock frequency: 50.000000 MHz
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12 | # Debug interface: FPGA JTAG
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13 | # On Chip Memory : 320 KB
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14 | # ##############################################################################
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15 |
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16 |
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17 | PARAMETER VERSION = 2.1.0
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18 |
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19 |
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20 | PORT fpga_0_LEDs_4Bit_GPIO_d_out_pin = fpga_0_LEDs_4Bit_GPIO_d_out, DIR = O, VEC = [0:3]
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21 | PORT fpga_0_Push_Buttons_4bit_GPIO_in_pin = fpga_0_Push_Buttons_4bit_GPIO_in, DIR = I, VEC = [0:3]
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22 | PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
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23 | PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
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24 | PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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25 | PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
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26 |
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27 |
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28 | BEGIN ppc405
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29 | PARAMETER INSTANCE = ppc405_0
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30 | PARAMETER HW_VER = 2.00.c
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31 | BUS_INTERFACE JTAGPPC = jtagppc_0_0
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32 | BUS_INTERFACE ISOCM = iocm
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33 | BUS_INTERFACE DSOCM = docm
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34 | BUS_INTERFACE IPLB = plb
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35 | BUS_INTERFACE DPLB = plb
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36 | PORT PLBCLK = sys_clk_s
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37 | PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
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38 | PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
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39 | PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
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40 | PORT RSTC405RESETCHIP = RSTC405RESETCHIP
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41 | PORT RSTC405RESETCORE = RSTC405RESETCORE
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42 | PORT RSTC405RESETSYS = RSTC405RESETSYS
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43 | PORT BRAMISOCMCLK = sys_clk_s
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44 | PORT BRAMDSOCMCLK = sys_clk_s
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45 | PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
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46 | PORT CPMC405CLOCK = proc_clk_s
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47 | END
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48 |
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49 | BEGIN ppc405
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50 | PARAMETER INSTANCE = ppc405_1
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51 | PARAMETER HW_VER = 2.00.c
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52 | BUS_INTERFACE JTAGPPC = jtagppc_0_1
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53 | END
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54 |
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55 | BEGIN jtagppc_cntlr
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56 | PARAMETER INSTANCE = jtagppc_0
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57 | PARAMETER HW_VER = 2.00.a
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58 | BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
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59 | BUS_INTERFACE JTAGPPC1 = jtagppc_0_1
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60 | END
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61 |
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62 | BEGIN proc_sys_reset
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63 | PARAMETER INSTANCE = reset_block
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64 | PARAMETER HW_VER = 1.00.a
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65 | PARAMETER C_EXT_RESET_HIGH = 1
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66 | PORT Ext_Reset_In = sys_rst_s
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67 | PORT Slowest_sync_clk = sys_clk_s
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68 | PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
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69 | PORT Core_Reset_Req = C405RSTCORERESETREQ
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70 | PORT System_Reset_Req = C405RSTSYSRESETREQ
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71 | PORT Rstc405resetchip = RSTC405RESETCHIP
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72 | PORT Rstc405resetcore = RSTC405RESETCORE
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73 | PORT Rstc405resetsys = RSTC405RESETSYS
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74 | PORT Bus_Struct_Reset = sys_bus_reset
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75 | PORT Dcm_locked = dcm_0_lock
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76 | END
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77 |
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78 | BEGIN isocm_v10
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79 | PARAMETER INSTANCE = iocm
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80 | PARAMETER HW_VER = 2.00.a
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81 | PARAMETER C_ISCNTLVALUE = 0x87
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82 | PORT ISOCM_Clk = sys_clk_s
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83 | PORT sys_rst = sys_bus_reset
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84 | END
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85 |
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86 | BEGIN isbram_if_cntlr
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87 | PARAMETER INSTANCE = iocm_cntlr
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88 | PARAMETER HW_VER = 3.00.a
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89 | PARAMETER C_BASEADDR = 0x00000000
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90 | PARAMETER C_HIGHADDR = 0x0001ffff
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91 | BUS_INTERFACE ISOCM = iocm
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92 | BUS_INTERFACE DCR_WRITE_PORT = isocm_porta
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93 | BUS_INTERFACE INSTRN_READ_PORT = isocm_portb
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94 | END
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95 |
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96 | BEGIN bram_block
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97 | PARAMETER INSTANCE = isocm_bram
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98 | PARAMETER HW_VER = 1.00.a
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99 | BUS_INTERFACE PORTA = isocm_porta
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100 | BUS_INTERFACE PORTB = isocm_portb
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101 | END
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102 |
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103 | BEGIN dsocm_v10
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104 | PARAMETER INSTANCE = docm
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105 | PARAMETER HW_VER = 2.00.a
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106 | PARAMETER C_DSCNTLVALUE = 0x87
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107 | PORT DSOCM_Clk = sys_clk_s
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108 | PORT sys_rst = sys_bus_reset
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109 | END
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110 |
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111 | BEGIN dsbram_if_cntlr
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112 | PARAMETER INSTANCE = docm_cntlr
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113 | PARAMETER HW_VER = 3.00.a
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114 | PARAMETER C_BASEADDR = 0x21800000
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115 | PARAMETER C_HIGHADDR = 0x2180ffff
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116 | BUS_INTERFACE DSOCM = docm
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117 | BUS_INTERFACE PORTA = dsocm_porta
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118 | END
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119 |
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120 | BEGIN bram_block
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121 | PARAMETER INSTANCE = dsocm_bram
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122 | PARAMETER HW_VER = 1.00.a
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123 | BUS_INTERFACE PORTA = dsocm_porta
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124 | END
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125 |
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126 | BEGIN plb_v34
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127 | PARAMETER INSTANCE = plb
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128 | PARAMETER HW_VER = 1.02.a
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129 | PARAMETER C_DCR_INTFCE = 0
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130 | PARAMETER C_EXT_RESET_HIGH = 1
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131 | PORT SYS_Rst = sys_bus_reset
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132 | PORT PLB_Clk = sys_clk_s
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133 | END
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134 |
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135 | BEGIN opb_v20
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136 | PARAMETER INSTANCE = opb
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137 | PARAMETER HW_VER = 1.10.c
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138 | PARAMETER C_EXT_RESET_HIGH = 1
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139 | PORT SYS_Rst = sys_bus_reset
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140 | PORT OPB_Clk = sys_clk_s
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141 | END
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142 |
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143 | BEGIN plb2opb_bridge
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144 | PARAMETER INSTANCE = plb2opb
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145 | PARAMETER HW_VER = 1.01.a
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146 | PARAMETER C_DCR_INTFCE = 0
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147 | PARAMETER C_RNG0_BASEADDR = 0x40000000
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148 | PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
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149 | PARAMETER C_NUM_ADDR_RNG = 1
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150 | BUS_INTERFACE SPLB = plb
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151 | BUS_INTERFACE MOPB = opb
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152 | END
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153 |
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154 | BEGIN opb_gpio
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155 | PARAMETER INSTANCE = LEDs_4Bit
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156 | PARAMETER HW_VER = 3.01.b
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157 | PARAMETER C_GPIO_WIDTH = 4
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158 | PARAMETER C_IS_DUAL = 0
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159 | PARAMETER C_IS_BIDIR = 0
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160 | PARAMETER C_ALL_INPUTS = 0
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161 | PARAMETER C_BASEADDR = 0x40020000
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162 | PARAMETER C_HIGHADDR = 0x4002ffff
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163 | BUS_INTERFACE SOPB = opb
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164 | PORT GPIO_d_out = fpga_0_LEDs_4Bit_GPIO_d_out
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165 | END
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166 |
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167 | BEGIN opb_gpio
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168 | PARAMETER INSTANCE = Push_Buttons_4bit
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169 | PARAMETER HW_VER = 3.01.b
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170 | PARAMETER C_INTERRUPT_PRESENT = 1
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171 | PARAMETER C_GPIO_WIDTH = 4
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172 | PARAMETER C_IS_DUAL = 0
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173 | PARAMETER C_IS_BIDIR = 0
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174 | PARAMETER C_ALL_INPUTS = 1
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175 | PARAMETER C_BASEADDR = 0x40000000
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176 | PARAMETER C_HIGHADDR = 0x4000ffff
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177 | BUS_INTERFACE SOPB = opb
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178 | PORT IP2INTC_Irpt = Push_Buttons_4bit_IP2INTC_Irpt
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179 | PORT GPIO_in = fpga_0_Push_Buttons_4bit_GPIO_in
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180 | END
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181 |
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182 | BEGIN opb_uartlite
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183 | PARAMETER INSTANCE = RS232
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184 | PARAMETER HW_VER = 1.00.b
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185 | PARAMETER C_BAUDRATE = 57600
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186 | PARAMETER C_DATA_BITS = 8
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187 | PARAMETER C_ODD_PARITY = 0
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188 | PARAMETER C_USE_PARITY = 0
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189 | PARAMETER C_CLK_FREQ = 50000000
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190 | PARAMETER C_BASEADDR = 0x40600000
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191 | PARAMETER C_HIGHADDR = 0x4060ffff
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192 | BUS_INTERFACE SOPB = opb
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193 | PORT RX = fpga_0_RS232_RX
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194 | PORT TX = fpga_0_RS232_TX
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195 | END
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196 |
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197 | BEGIN plb_bram_if_cntlr
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198 | PARAMETER INSTANCE = plb_bram_if_cntlr_1
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199 | PARAMETER HW_VER = 1.00.b
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200 | PARAMETER c_plb_clk_period_ps = 20000
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201 | PARAMETER c_baseaddr = 0xfffe0000
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202 | PARAMETER c_highaddr = 0xffffffff
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203 | BUS_INTERFACE SPLB = plb
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204 | BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
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205 | END
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206 |
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207 | BEGIN bram_block
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208 | PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
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209 | PARAMETER HW_VER = 1.00.a
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210 | BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
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211 | END
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212 |
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213 | BEGIN opb_intc
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214 | PARAMETER INSTANCE = opb_intc_0
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215 | PARAMETER HW_VER = 1.00.c
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216 | PARAMETER C_BASEADDR = 0x41200000
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217 | PARAMETER C_HIGHADDR = 0x4120ffff
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218 | BUS_INTERFACE SOPB = opb
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219 | PORT Irq = EICC405EXTINPUTIRQ
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220 | PORT Intr = Push_Buttons_4bit_IP2INTC_Irpt&opb_timer_0_Interrupt
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221 | END
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222 |
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223 | BEGIN dcm_module
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224 | PARAMETER INSTANCE = dcm_0
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225 | PARAMETER HW_VER = 1.00.a
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226 | PARAMETER C_CLK0_BUF = TRUE
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227 | PARAMETER C_CLK2X_BUF = TRUE
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228 | PARAMETER C_CLKDV_BUF = TRUE
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229 | PARAMETER C_CLKDV_DIVIDE = 2.000000
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230 | PARAMETER C_CLKIN_PERIOD = 10.000000
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231 | PARAMETER C_CLK_FEEDBACK = 1X
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232 | PARAMETER C_DLL_FREQUENCY_MODE = LOW
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233 | PARAMETER C_EXT_RESET_HIGH = 1
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234 | PORT CLKIN = dcm_clk_s
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235 | PORT CLK2X = proc_clk_s
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236 | PORT CLKDV = sys_clk_s
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237 | PORT CLK0 = dcm_0_FB
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238 | PORT CLKFB = dcm_0_FB
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239 | PORT RST = net_gnd
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240 | PORT LOCKED = dcm_0_lock
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241 | END
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242 |
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243 | BEGIN opb_timer
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244 | PARAMETER INSTANCE = opb_timer_0
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245 | PARAMETER HW_VER = 1.00.b
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246 | PARAMETER C_BASEADDR = 0x41c00000
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247 | PARAMETER C_HIGHADDR = 0x41c0ffff
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248 | BUS_INTERFACE SOPB = opb
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249 | PORT Interrupt = opb_timer_0_Interrupt
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250 | END
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251 |
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