source:
Hardware/WARP_v3/Rev1.1/Config_CPLD/src/spi_boot_OpenCores_src/rtl/vhdl
Name | Size | Rev | Age | Author | Last Change |
---|---|---|---|---|---|
../ | |||||
sample | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … | |
chip-e.vhd | 3.0 KB | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
chip-full-a.vhd | 5.6 KB | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
chip-full-c.vhd | 419 bytes | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
chip-minimal-a.vhd | 5.6 KB | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
chip-minimal-c.vhd | 431 bytes | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
chip-mmc-a.vhd | 5.6 KB | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
chip-mmc-c.vhd | 415 bytes | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
chip-sd-a.vhd | 5.6 KB | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
chip-sd-c.vhd | 411 bytes | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
spi_boot-c.vhd | 597 bytes | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
spi_boot.vhd | 28.6 KB | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
spi_boot_pack-p.vhd | 844 bytes | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
spi_counter-c.vhd | 348 bytes | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
spi_counter.vhd | 3.3 KB | 1799 | 12 years | murphpo | Adding WARP v3 hardware files (schematics, FPGA pinout, configuration … |
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