[553] | 1 | ###################################################################
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| 2 | ##
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| 3 | ## Name : clock_board_config
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| 4 | ## Desc : Microprocessor Peripheral Description
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| 5 | ## : Automatically generated by PsfUtility
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| 6 | ##
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| 7 | ###################################################################
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| 8 |
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| 9 | BEGIN clock_board_config
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| 10 |
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| 11 | ## Peripheral Options
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| 12 | OPTION IPTYPE = PERIPHERAL
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| 13 | OPTION IMP_NETLIST = TRUE
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| 14 | OPTION HDL = VERILOG
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[1695] | 15 | OPTION USAGE_LEVEL = BASE_USER
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| 16 | OPTION DESC = WARP Clock Board Configuration Core
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| 17 | OPTION LONG_DESC = "Configures the Clock Board after FPGA configuration- requied to use the Clock Board oscillators as the master FPGA clock, sampling clock for Radio Boards and RF refence clock for Radio Boards."
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[553] | 18 | OPTION IP_GROUP = USER
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[1695] | 19 | OPTION ARCH_SUPPORT_MAP = (virtex4=PREFERRED, virtex2p=PREFERRED, others=AVAILABLE)
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| 20 | OPTION RUN_NGCBUILD = FALSE
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| 21 | OPTION STYLE = HDL
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[553] | 22 |
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[1695] | 23 | IO_INTERFACE IO_IF = clock_board_config, IO_TYPE = WARP_CLKBRD_CONFIG_V1
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[553] | 24 |
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| 25 | ## Bus Interfaces
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[621] | 26 | # This core is not attached to any busses
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[553] | 27 |
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| 28 | ## Generics for VHDL or Parameters for Verilog
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| 29 |
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[1559] | 30 | PARAMETER radio_clk_source_sel_mode = 0, DT = std_logic, DESC = Selects whether to use radio_clk_src_sel port at boot to select radio RF clock source, VALUES = (0=Use Parameter, 1=Use Port), PERMIT = BASE_USER
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| 31 | PARAMETER logic_clk_source_sel_mode = 0, DT = std_logic, DESC = Selects whether to use logic_clk_src_sel port at boot to select sampling clock source, VALUES = (0=Use Parameter, 1=Use Port), PERMIT = BASE_USER
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[1481] | 32 |
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[621] | 33 | #platgen will infer these hex values and defparam them in the Verilog like "defparam clkbrdconfig_0.fpga_radio_clk_source = 'h1AFF;"
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| 34 | #since they're 16 bits anyway, the ambiguous bit length in the defparam'd value is no problem
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[1484] | 35 | #PARAMETER fpga_radio_clk_source = 0x1AFF, DT = std_logic_vector, DESC = Selects radio reference clock source, VALUES = (0x1AFF=Oscillator, 0x1DFF=External Coax), PERMIT = BASE_USER
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| 36 | #PARAMETER fpga_logic_clk_source = 0x1AFF, DT = std_logic_vector, DESC = Selects FPGA/sampling clock source, VALUES = (0x1AFF=Oscillator, 0x1DFF=External Coax), PERMIT = BASE_USER
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| 37 | PARAMETER fpga_radio_clk_source = 0, DT = std_logic, DESC = Selects radio reference clock source, VALUES = (0=Oscillator, 1=External Coax), PERMIT = BASE_USER
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| 38 | PARAMETER fpga_logic_clk_source = 0, DT = std_logic, DESC = Selects FPGA/sampling clock source, VALUES = (0=Oscillator, 1=External Coax), PERMIT = BASE_USER
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[621] | 39 |
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[847] | 40 | # Parameters controlling en/disable on radio reference clk outputs
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| 41 | # 0x01ff disables the corresponding output
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| 42 | # 0x1eff enables the corresponding ouptput
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| 43 | # By default, outputs for slots 2 and 3 are enabled, matching
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| 44 | # the hardware config for a WARP MIMO kit
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[901] | 45 | PARAMETER radio_clk_out4_mode = 0x01ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock on J12 - disabled by default, VALUES = (0x01ff=Disabled, 0x1eff=Enabled), PERMIT = BASE_USER
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| 46 | PARAMETER radio_clk_out5_mode = 0x1eff, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock on J11 - disabled by default, VALUES = (0x01ff=Disabled, 0x1eff=Enabled), PERMIT = BASE_USER
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| 47 | PARAMETER radio_clk_out6_mode = 0x1eff, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock on J10 - disabled by default, VALUES = (0x01ff=Disabled, 0x1eff=Enabled), PERMIT = BASE_USER
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| 48 | PARAMETER radio_clk_out7_mode = 0x01ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock on J6 - disabled by default, VALUES = (0x01ff=Disabled, 0x1eff=Enabled), PERMIT = BASE_USER
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[847] | 49 |
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| 50 | # Parameters controlling en/disable on radio sampling clk outputs
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| 51 | # 0x02ff disables the corresponding output
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| 52 | # 0x04ff enables the corresponding output with min (340mV) drive
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| 53 | # 0x08ff enables the corresponding output with max (810mV) drive
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| 54 | # By default, outputs for slots 2 and 3 are enabled, matching
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| 55 | # the hardware config for a WARP MIMO kit
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[902] | 56 | PARAMETER logic_clk_out0_mode = 0x02ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock on J8 - disabled by default, VALUES = (0x02ff=Disabled, 0x04ff=Enabled - 340mV drive, 0x00ff=Enabled - 500mV drive, 0x0Cff=Enabled - 660mV drive, 0x08ff=Enabled - 810mV drive), PERMIT = BASE_USER
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| 57 | PARAMETER logic_clk_out1_mode = 0x02ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock on J7 - disabled by default, VALUES = (0x02ff=Disabled, 0x04ff=Enabled - 340mV drive, 0x00ff=Enabled - 500mV drive, 0x0Cff=Enabled - 660mV drive, 0x08ff=Enabled - 810mV drive), PERMIT = BASE_USER
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| 58 | PARAMETER logic_clk_out2_mode = 0x08ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock on J9 - 810mV drive by default, VALUES = (0x02ff=Disabled, 0x04ff=Enabled - 340mV drive, 0x00ff=Enabled - 500mV drive, 0x0Cff=Enabled - 660mV drive, 0x08ff=Enabled - 810mV drive), PERMIT = BASE_USER
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[901] | 59 | PARAMETER logic_clk_out3_mode = 0x08ff, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock on J13 - 810mV drive by default, VALUES = (0x02ff=Disabled, 0x04ff=Enabled - 340mV drive, 0x00ff=Enabled - 500mV drive, 0x0Cff=Enabled - 660mV drive, 0x08ff=Enabled - 810mV drive), PERMIT = BASE_USER
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[847] | 60 |
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[898] | 61 | # Parameters controlling the clock outputs for off-board use
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| 62 | # These ports are only used when sharing clocks between nodes
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| 63 | PARAMETER radio_clk_forward_out_mode = 0x0BFF, DT = std_logic_vector, DESC = Selects whether to enable or disable the radio reference clock forward port for off-board use - disabled by default, VALUES = (0x0BFF=Disabled, 0x08FF=Enabled), PERMIT = BASE_USER
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| 64 | PARAMETER logic_clk_forward_out_mode = 0x1FFF, DT = std_logic_vector, DESC = Selects whether to enable or disable the sampling clock forward port for off-board use - disabled by default, VALUES = (0x1FFF=Disabled, 0x1EFF=Enabled), PERMIT = BASE_USER
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[847] | 65 |
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[621] | 66 | PARAMETER sys_clk_freq_hz = 0x05f5e100, DT = std_logic_vector, DESC = Frequency of clock at sys_clk input, VALUES = (0x05f5e100=100MHz, 0x1F78A40=33MHz), PERMIT = BASE_USER
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| 67 | PARAMETER scp_min_freq_hz = 0x002625a0, DT = std_logic_vector, DESC = Minimum serial I/O frequency, VALUES = (0x002625a0=25MHz), PERMIT = BASE_USER
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| 68 |
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| 69 | PARAMETER scp_cyc_leng_a = 0x00000028, DT = std_logic_vector, DESC = Length of serial I/O write cycle, VALUES = (0x00000028=40), PERMIT = BASE_USER
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| 70 | PARAMETER scp_cyc_leng_b = 0x00000028, DT = std_logic_vector, DESC = Length of serial I/O write cycle, VALUES = (0x00000028=40), PERMIT = BASE_USER
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| 71 | PARAMETER scp_cyc_leng = 0x00000028, DT = std_logic_vector, DESC = Length of serial I/O write cycle, VALUES = (0x00000028=40), PERMIT = BASE_USER
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| 72 |
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[553] | 73 | ## Ports
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[1695] | 74 | PORT sys_clk = "", DIR = I, SIGIS = CLK, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_CLKIN, PERMIT = BASE_USER
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| 75 | PORT sys_rst = "net_gnd", DIR = I, SIGIS = RST, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_RST, PERMIT = BASE_USER
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| 76 | PORT cfg_radio_dat_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_RFDOUT, PERMIT = BASE_USER
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| 77 | PORT cfg_radio_csb_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_RFCS, PERMIT = BASE_USER
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| 78 | PORT cfg_radio_en_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_RFEN, PERMIT = BASE_USER
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| 79 | PORT cfg_radio_clk_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_RFSCLK, PERMIT = BASE_USER
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| 80 | PORT cfg_logic_dat_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_SAMPDOUT, PERMIT = BASE_USER
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| 81 | PORT cfg_logic_csb_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_SAMPCS, PERMIT = BASE_USER
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| 82 | PORT cfg_logic_en_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_SAMPEN, PERMIT = BASE_USER
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| 83 | PORT cfg_logic_clk_out = "", DIR = O, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_SAMPSCLK, PERMIT = BASE_USER
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[553] | 84 |
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[1695] | 85 | PORT radio_clk_src_sel = "net_gnd", DIR = I, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_RFSRCSEL, PERMIT = BASE_USER
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| 86 | PORT logic_clk_src_sel = "net_gnd", DIR = I, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_SAMPSRCSEL, PERMIT = BASE_USER
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[1481] | 87 |
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| 88 |
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[1348] | 89 | #This output must be connected to the reset of the project's
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| 90 | # clock generator, in order to hold the system's DCMs in reset
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| 91 | # until the clock board outputs are providing valid clock signals
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[1695] | 92 | #Unfortunately it seems BSB can't make this connection automatically,
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| 93 | # since BSB infers the DCM later, when instantiating the clock_genertor
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| 94 | #The ASSIGNMENT=REQUIRE here throws an early error on purpose
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| 95 | # (vs. waiting to see things not work in hardware)
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| 96 | PORT config_invalid = "", DIR = O, ASSIGNMENT = REQUIRE, SIGIS = RST, IO_IF = clock_board_config, IO_IS=CLKBRDCFG_CLKINV, PERMIT = BASE_USER
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[553] | 97 |
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| 98 | END
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