| 1 | ###################################################################
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| 2 | ##
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| 3 | ## Name : null_pair_example
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| 4 | ## Desc : Microprocessor Peripheral Description
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| 5 | ## : Automatically generated by PsfUtility
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| 6 | ##
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| 7 | ###################################################################
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| 8 |
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| 9 | BEGIN mgt_null_controller
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| 10 |
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| 11 | ## Peripheral Options
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| 12 | OPTION IPTYPE = PERIPHERAL
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| 13 | OPTION IMP_NETLIST = TRUE
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| 14 | OPTION HDL = VERILOG
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| 15 | OPTION ARCH_SUPPORT_MAP = (virtex4=DEVELOPMENT, others=OBSOLETE)
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| 16 | OPTION IP_GROUP = USER
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| 17 | OPTION STYLE = MIX
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| 18 | OPTION RUN_NGCBUILD = TRUE
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| 19 |
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| 20 | PARAMETER enable_null_mgt02 = 1, DT = INTEGER, DESC = Enable Null MGT Wrapper for Tile 102, VALUES = (0=Disable, 1=Enable), PERMIT = BASE_USER
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| 21 | PARAMETER enable_null_mgt12 = 1, DT = INTEGER, DESC = Enable Null MGT Wrapper for Tile 112, VALUES = (0=Disable, 1=Enable), PERMIT = BASE_USER
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| 22 | PARAMETER enable_null_mgt13 = 1, DT = INTEGER, DESC = Enable Null MGT Wrapper for Tile 113, VALUES = (0=Disable, 1=Enable), PERMIT = BASE_USER
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| 23 | PARAMETER enable_null_mgt14 = 1, DT = INTEGER, DESC = Enable Null MGT Wrapper for Tile 114, VALUES = (0=Disable, 1=Enable), PERMIT = BASE_USER
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| 24 |
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| 25 | ## Bus Interfaces
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| 26 |
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| 27 | ## Generics for VHDL or Parameters for Verilog
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| 28 |
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| 29 | ## Ports
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| 30 | PORT grefclk = "", DIR = I
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| 31 | PORT rxn_mgt01 = "", DIR = I, VEC = [0:1]
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| 32 | PORT rxp_mgt01 = "", DIR = I, VEC = [0:1]
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| 33 | PORT txn_mgt01 = "", DIR = O, VEC = [0:1]
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| 34 | PORT txp_mgt01 = "", DIR = O, VEC = [0:1]
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| 35 | PORT rxn_mgt02 = "", DIR = I, VEC = [0:1]
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| 36 | PORT rxp_mgt02 = "", DIR = I, VEC = [0:1]
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| 37 | PORT txn_mgt02 = "", DIR = O, VEC = [0:1]
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| 38 | PORT txp_mgt02 = "", DIR = O, VEC = [0:1]
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| 39 | PORT rxn_mgt03 = "", DIR = I, VEC = [0:1]
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| 40 | PORT rxp_mgt03 = "", DIR = I, VEC = [0:1]
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| 41 | PORT txn_mgt03 = "", DIR = O, VEC = [0:1]
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| 42 | PORT txp_mgt03 = "", DIR = O, VEC = [0:1]
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| 43 | PORT rxn_mgt05 = "", DIR = I, VEC = [0:1]
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| 44 | PORT rxp_mgt05 = "", DIR = I, VEC = [0:1]
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| 45 | PORT txn_mgt05 = "", DIR = O, VEC = [0:1]
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| 46 | PORT txp_mgt05 = "", DIR = O, VEC = [0:1]
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| 47 | PORT rxn_mgt06 = "", DIR = I, VEC = [0:1]
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| 48 | PORT rxp_mgt06 = "", DIR = I, VEC = [0:1]
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| 49 | PORT txn_mgt06 = "", DIR = O, VEC = [0:1]
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| 50 | PORT txp_mgt06 = "", DIR = O, VEC = [0:1]
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| 51 | PORT rxn_mgt09 = "", DIR = I, VEC = [0:1]
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| 52 | PORT rxp_mgt09 = "", DIR = I, VEC = [0:1]
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| 53 | PORT txn_mgt09 = "", DIR = O, VEC = [0:1]
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| 54 | PORT txp_mgt09 = "", DIR = O, VEC = [0:1]
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| 55 | PORT rxn_mgt10 = "", DIR = I, VEC = [0:1]
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| 56 | PORT rxp_mgt10 = "", DIR = I, VEC = [0:1]
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| 57 | PORT txn_mgt10 = "", DIR = O, VEC = [0:1]
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| 58 | PORT txp_mgt10 = "", DIR = O, VEC = [0:1]
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| 59 | PORT rxn_mgt12 = "", DIR = I, VEC = [0:1]
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| 60 | PORT rxp_mgt12 = "", DIR = I, VEC = [0:1]
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| 61 | PORT txn_mgt12 = "", DIR = O, VEC = [0:1]
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| 62 | PORT txp_mgt12 = "", DIR = O, VEC = [0:1]
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| 63 | PORT rxn_mgt13 = "", DIR = I, VEC = [0:1]
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| 64 | PORT rxp_mgt13 = "", DIR = I, VEC = [0:1]
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| 65 | PORT txn_mgt13 = "", DIR = O, VEC = [0:1]
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| 66 | PORT txp_mgt13 = "", DIR = O, VEC = [0:1]
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| 67 | PORT rxn_mgt14 = "", DIR = I, VEC = [0:1]
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| 68 | PORT rxp_mgt14 = "", DIR = I, VEC = [0:1]
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| 69 | PORT txn_mgt14 = "", DIR = O, VEC = [0:1]
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| 70 | PORT txp_mgt14 = "", DIR = O, VEC = [0:1]
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| 71 |
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| 72 | END
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