[1927] | 1 | //---------------------------------------------------------------------------- |
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| 2 | // user_logic.v - module |
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| 3 | //---------------------------------------------------------------------------- |
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| 4 | // |
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| 5 | // *************************************************************************** |
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| 6 | // ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** |
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| 7 | // ** ** |
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| 8 | // ** Xilinx, Inc. ** |
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| 9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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| 10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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| 11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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| 12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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| 13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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| 14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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| 15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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| 16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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| 17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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| 18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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| 19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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| 20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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| 21 | // ** FOR A PARTICULAR PURPOSE. ** |
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| 22 | // ** ** |
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| 23 | // *************************************************************************** |
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| 24 | // |
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| 25 | //---------------------------------------------------------------------------- |
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| 26 | // Filename: user_logic.v |
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| 27 | // Version: 3.00.c |
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| 28 | // Description: User logic module. |
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| 29 | // Date: Tue Feb 26 20:52:28 2013 (by Create and Import Peripheral Wizard) |
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| 30 | // Verilog Standard: Verilog-2001 |
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| 31 | //---------------------------------------------------------------------------- |
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| 32 | // Naming Conventions: |
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| 33 | // active low signals: "*_n" |
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| 34 | // clock signals: "clk", "clk_div#", "clk_#x" |
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| 35 | // reset signals: "rst", "rst_n" |
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| 36 | // generics: "C_*" |
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| 37 | // user defined types: "*_TYPE" |
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| 38 | // state machine next state: "*_ns" |
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| 39 | // state machine current state: "*_cs" |
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| 40 | // combinatorial signals: "*_com" |
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| 41 | // pipelined or register delay signals: "*_d#" |
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| 42 | // counter signals: "*cnt*" |
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| 43 | // clock enable signals: "*_ce" |
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| 44 | // internal version of output port: "*_i" |
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| 45 | // device pins: "*_pin" |
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| 46 | // ports: "- Names begin with Uppercase" |
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| 47 | // processes: "*_PROCESS" |
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| 48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
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| 49 | //---------------------------------------------------------------------------- |
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| 50 | |
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| 51 | `uselib lib=unisims_ver |
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| 52 | `uselib lib=proc_common_v3_00_a |
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| 53 | |
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| 54 | module user_logic |
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| 55 | ( |
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| 56 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
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| 57 | //I/O for MAX2829 pins |
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[2906] | 58 | output reg RFA_TxEn, |
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| 59 | output reg RFB_TxEn, |
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| 60 | output reg RFC_TxEn, |
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| 61 | output reg RFD_TxEn, |
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[1927] | 62 | |
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[2906] | 63 | output reg RFA_RxEn, |
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| 64 | output reg RFB_RxEn, |
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| 65 | output reg RFC_RxEn, |
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| 66 | output reg RFD_RxEn, |
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[1927] | 67 | |
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[2906] | 68 | output reg RFA_RxHP, |
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| 69 | output reg RFB_RxHP, |
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| 70 | output reg RFC_RxHP, |
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| 71 | output reg RFD_RxHP, |
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[1927] | 72 | |
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[2906] | 73 | output reg RFA_SHDN, |
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| 74 | output reg RFB_SHDN, |
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| 75 | output reg RFC_SHDN, |
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| 76 | output reg RFD_SHDN, |
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[1927] | 77 | |
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| 78 | output RFA_SPI_SCLK, |
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| 79 | output RFB_SPI_SCLK, |
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| 80 | output RFC_SPI_SCLK, |
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| 81 | output RFD_SPI_SCLK, |
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| 82 | |
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| 83 | output RFA_SPI_MOSI, |
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| 84 | output RFB_SPI_MOSI, |
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| 85 | output RFC_SPI_MOSI, |
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| 86 | output RFD_SPI_MOSI, |
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| 87 | |
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| 88 | output RFA_SPI_CSn, |
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| 89 | output RFB_SPI_CSn, |
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| 90 | output RFC_SPI_CSn, |
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| 91 | output RFD_SPI_CSn, |
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| 92 | |
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[2906] | 93 | output reg [6:0] RFA_B, |
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| 94 | output reg [6:0] RFB_B, |
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| 95 | output reg [6:0] RFC_B, |
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| 96 | output reg [6:0] RFD_B, |
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[1927] | 97 | |
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| 98 | input RFA_LD, |
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| 99 | input RFB_LD, |
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| 100 | input RFC_LD, |
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| 101 | input RFD_LD, |
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| 102 | |
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| 103 | //Outputs to PA and ant switch pins |
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[2906] | 104 | output reg RFA_PAEn_24, |
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| 105 | output reg RFB_PAEn_24, |
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| 106 | output reg RFC_PAEn_24, |
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| 107 | output reg RFD_PAEn_24, |
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[1927] | 108 | |
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[2906] | 109 | output reg RFA_PAEn_5, |
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| 110 | output reg RFB_PAEn_5, |
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| 111 | output reg RFC_PAEn_5, |
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| 112 | output reg RFD_PAEn_5, |
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[1927] | 113 | |
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[2906] | 114 | output reg [1:0] RFA_AntSw, |
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| 115 | output reg [1:0] RFB_AntSw, |
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| 116 | output reg [1:0] RFC_AntSw, |
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| 117 | output reg [1:0] RFD_AntSw, |
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[1927] | 118 | |
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| 119 | //I/O for user logic to control state from hardware |
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| 120 | input usr_RFA_TxEn, |
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| 121 | input usr_RFB_TxEn, |
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| 122 | input usr_RFC_TxEn, |
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| 123 | input usr_RFD_TxEn, |
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| 124 | |
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| 125 | input usr_RFA_RxEn, |
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| 126 | input usr_RFB_RxEn, |
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| 127 | input usr_RFC_RxEn, |
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| 128 | input usr_RFD_RxEn, |
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| 129 | |
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| 130 | input usr_RFA_RxHP, |
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| 131 | input usr_RFB_RxHP, |
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| 132 | input usr_RFC_RxHP, |
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| 133 | input usr_RFD_RxHP, |
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| 134 | |
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| 135 | input usr_RFA_SHDN, |
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| 136 | input usr_RFB_SHDN, |
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| 137 | input usr_RFC_SHDN, |
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| 138 | input usr_RFD_SHDN, |
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| 139 | |
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| 140 | input [1:0] usr_RFA_RxGainRF, |
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| 141 | input [1:0] usr_RFB_RxGainRF, |
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| 142 | input [1:0] usr_RFC_RxGainRF, |
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| 143 | input [1:0] usr_RFD_RxGainRF, |
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| 144 | |
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| 145 | input [4:0] usr_RFA_RxGainBB, |
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| 146 | input [4:0] usr_RFB_RxGainBB, |
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| 147 | input [4:0] usr_RFC_RxGainBB, |
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| 148 | input [4:0] usr_RFD_RxGainBB, |
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| 149 | |
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| 150 | input [5:0] usr_RFA_TxGain, |
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| 151 | input [5:0] usr_RFB_TxGain, |
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| 152 | input [5:0] usr_RFC_TxGain, |
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| 153 | input [5:0] usr_RFD_TxGain, |
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| 154 | |
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| 155 | input usr_SPI_ctrlSrc, |
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| 156 | input usr_SPI_go, |
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| 157 | output usr_SPI_active, |
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| 158 | input [3:0] usr_SPI_rfsel, |
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| 159 | input [3:0] usr_SPI_regaddr, |
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| 160 | input [13:0] usr_SPI_regdata, |
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| 161 | |
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| 162 | output usr_RFA_PHYStart, |
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| 163 | output usr_RFB_PHYStart, |
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| 164 | output usr_RFC_PHYStart, |
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| 165 | output usr_RFD_PHYStart, |
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| 166 | |
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| 167 | output usr_any_PHYStart, |
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| 168 | |
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[2906] | 169 | output reg usr_RFA_statLED_Tx, |
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| 170 | output reg usr_RFA_statLED_Rx, |
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| 171 | output reg usr_RFB_statLED_Tx, |
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| 172 | output reg usr_RFB_statLED_Rx, |
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| 173 | output reg usr_RFC_statLED_Tx, |
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| 174 | output reg usr_RFC_statLED_Rx, |
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| 175 | output reg usr_RFD_statLED_Tx, |
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| 176 | output reg usr_RFD_statLED_Rx, |
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[1927] | 177 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
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| 178 | |
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| 179 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
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| 180 | // -- Bus protocol ports, do not add to or delete |
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| 181 | input Bus2IP_Clk, |
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| 182 | input Bus2IP_Resetn, |
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| 183 | input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data, |
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| 184 | input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE, |
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| 185 | input [C_NUM_REG-1 : 0] Bus2IP_RdCE, |
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| 186 | input [C_NUM_REG-1 : 0] Bus2IP_WrCE, |
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| 187 | output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data, |
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| 188 | output IP2Bus_RdAck, |
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| 189 | output IP2Bus_WrAck, |
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| 190 | output IP2Bus_Error |
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| 191 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
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| 192 | ); // user_logic |
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| 193 | |
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| 194 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
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| 195 | // --USER parameters added here |
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| 196 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
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| 197 | |
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| 198 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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| 199 | // -- Bus protocol parameters, do not add to or delete |
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| 200 | //parameter C_NUM_REG = 30; |
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| 201 | parameter C_NUM_REG = 64; |
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| 202 | parameter C_SLV_DWIDTH = 32; |
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| 203 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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| 204 | |
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| 205 | // -- ADD USER PORTS BELOW THIS LINE ----------------- |
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| 206 | // --USER ports added here |
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| 207 | // -- ADD USER PORTS ABOVE THIS LINE ----------------- |
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| 208 | |
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| 209 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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| 210 | // -- Bus protocol ports, do not add to or delete |
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| 211 | /* Moved to module declaration above |
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| 212 | input Bus2IP_Clk; |
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| 213 | input Bus2IP_Resetn; |
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| 214 | input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data; |
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| 215 | input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE; |
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| 216 | input [C_NUM_REG-1 : 0] Bus2IP_RdCE; |
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| 217 | input [C_NUM_REG-1 : 0] Bus2IP_WrCE; |
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| 218 | output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data; |
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| 219 | output IP2Bus_RdAck; |
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| 220 | output IP2Bus_WrAck; |
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| 221 | output IP2Bus_Error; |
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| 222 | */ |
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| 223 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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| 224 | |
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| 225 | //---------------------------------------------------------------------------- |
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| 226 | // Implementation |
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| 227 | //---------------------------------------------------------------------------- |
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| 228 | |
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| 229 | // --USER nets declarations added here, as needed for user logic |
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[2066] | 230 | `define TXTIMING_REG_ON_RESET 32'h10305020 //Sane default Tx Timing values |
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[1927] | 231 | `define TXGAINS_REG_ON_RESET 32'h32323232 //Tx Gain targets = 50 |
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| 232 | `define CLKDIV_GAINTIMING_REG_ON_RESET 32'h00004F22 //Gain step=0xF, time step=4, clk divs = 2 |
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| 233 | |
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| 234 | // Nets for user logic slave model s/w accessible register example |
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| 235 | reg [C_SLV_DWIDTH-1 : 0] slv_reg0; |
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| 236 | reg [C_SLV_DWIDTH-1 : 0] slv_reg1; |
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| 237 | reg [C_SLV_DWIDTH-1 : 0] slv_reg2; |
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| 238 | reg [C_SLV_DWIDTH-1 : 0] slv_reg3; |
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| 239 | reg [C_SLV_DWIDTH-1 : 0] slv_reg4; |
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| 240 | reg [C_SLV_DWIDTH-1 : 0] slv_reg5; |
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| 241 | reg [C_SLV_DWIDTH-1 : 0] slv_reg6; |
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| 242 | reg [C_SLV_DWIDTH-1 : 0] slv_reg7; |
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| 243 | reg [C_SLV_DWIDTH-1 : 0] slv_reg8; |
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| 244 | reg [C_SLV_DWIDTH-1 : 0] slv_reg9; |
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| 245 | reg [C_SLV_DWIDTH-1 : 0] slv_reg10; |
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| 246 | |
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| 247 | wire [10 : 0] slv_reg_write_sel; |
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| 248 | wire [63 : 0] slv_reg_read_sel; |
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| 249 | reg [C_SLV_DWIDTH-1 : 0] slv_ip2bus_data; |
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| 250 | wire slv_read_ack; |
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| 251 | wire slv_write_ack; |
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| 252 | integer byte_index, bit_index; |
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| 253 | |
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| 254 | wire slv_write_ack_normalRegisters; |
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| 255 | |
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| 256 | wire [31:0] status_reg; |
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| 257 | |
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| 258 | //Use Verilog array-of-arrays syntax for the register banks to mirror MAX2829 internal registers |
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| 259 | // RFx_MAX2829_mirrorRegs[N] maps to MAX2829 reg N, for N=[0x0, 0xC] |
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| 260 | // All registers are 14 bits in the MAX2829 |
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[2906] | 261 | wire [13:0] RFA_mirrorReg_data [12:0]; |
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| 262 | wire [13:0] RFB_mirrorReg_data [12:0]; |
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| 263 | wire [13:0] RFC_mirrorReg_data [12:0]; |
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| 264 | wire [13:0] RFD_mirrorReg_data [12:0]; |
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[1927] | 265 | |
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| 266 | wire RFA_TxEn_ctrlSrc, RFB_TxEn_ctrlSrc, RFC_TxEn_ctrlSrc, RFD_TxEn_ctrlSrc; |
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| 267 | wire RFA_RxEn_ctrlSrc, RFB_RxEn_ctrlSrc, RFC_RxEn_ctrlSrc, RFD_RxEn_ctrlSrc; |
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| 268 | wire RFA_RxHP_ctrlSrc, RFB_RxHP_ctrlSrc, RFC_RxHP_ctrlSrc, RFD_RxHP_ctrlSrc; |
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| 269 | wire RFA_SHDN_ctrlSrc, RFB_SHDN_ctrlSrc, RFC_SHDN_ctrlSrc, RFD_SHDN_ctrlSrc; |
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| 270 | wire RFA_TxGain_ctrlSrc, RFB_TxGain_ctrlSrc, RFC_TxGain_ctrlSrc, RFD_TxGain_ctrlSrc; |
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| 271 | wire RFA_RxGain_ctrlSrc, RFB_RxGain_ctrlSrc, RFC_RxGain_ctrlSrc, RFD_RxGain_ctrlSrc; |
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| 272 | |
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| 273 | wire RFA_TxEn_sw, RFB_TxEn_sw, RFC_TxEn_sw, RFD_TxEn_sw; |
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| 274 | wire RFA_RxEn_sw, RFB_RxEn_sw, RFC_RxEn_sw, RFD_RxEn_sw; |
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| 275 | wire RFA_RxHP_sw, RFB_RxHP_sw, RFC_RxHP_sw, RFD_RxHP_sw; |
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| 276 | wire RFA_SHDN_sw, RFB_SHDN_sw, RFC_SHDN_sw, RFD_SHDN_sw; |
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| 277 | |
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| 278 | wire RFA_PAEn, RFB_PAEn, RFC_PAEn, RFD_PAEn; |
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| 279 | |
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| 280 | wire [7:0] TxTiming_dly_TxGainRamp, TxTiming_dly_PowerAmpEn, TxTiming_dly_TxEn, TxTiming_dly_startPHY; |
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| 281 | |
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| 282 | wire [3:0] TxGainRamp_gainStep, TxGainRamp_timeStep; |
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| 283 | |
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| 284 | wire [5:0] RFA_TxGain_sw, RFB_TxGain_sw, RFC_TxGain_sw, RFD_TxGain_sw; |
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| 285 | wire [4:0] RFA_RxGainBB_sw, RFB_RxGainBB_sw, RFC_RxGainBB_sw, RFD_RxGainBB_sw; |
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| 286 | wire [1:0] RFA_RxGainRF_sw, RFB_RxGainRF_sw, RFC_RxGainRF_sw, RFD_RxGainRF_sw; |
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| 287 | |
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| 288 | wire [5:0] RFA_TxGain_target, RFB_TxGain_target, RFC_TxGain_target, RFD_TxGain_target; |
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| 289 | wire [5:0] RFA_TxGain_ramped, RFB_TxGain_ramped, RFC_TxGain_ramped, RFD_TxGain_ramped; |
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| 290 | |
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| 291 | wire [4:0] RFA_RxGainBB, RFB_RxGainBB, RFC_RxGainBB, RFD_RxGainBB; |
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| 292 | wire [1:0] RFA_RxGainRF, RFB_RxGainRF, RFC_RxGainRF, RFD_RxGainRF; |
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| 293 | |
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| 294 | wire [2:0] spi_clk_div_sel; |
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| 295 | wire [1:0] txTiming_clk_div_sel; |
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| 296 | |
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| 297 | wire [3:0] spi_rfsel_mask_sw; |
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| 298 | wire [3:0] spi_rfsel_mask; |
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| 299 | wire [13:0] spi_tx_regdata; |
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| 300 | wire [3:0] spi_tx_regaddr; |
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| 301 | wire spi_go; |
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| 302 | |
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| 303 | wire spi_tx_reg_write; |
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| 304 | wire spi_xfer_done; |
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| 305 | |
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| 306 | wire RFA_txStart, RFB_txStart, RFC_txStart, RFD_txStart; |
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| 307 | |
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| 308 | wire RFA_MAX2829_Reset, RFB_MAX2829_Reset, RFC_MAX2829_Reset, RFD_MAX2829_Reset; |
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[2906] | 309 | reg RFA_MAX2829_Reset_d, RFB_MAX2829_Reset_d, RFC_MAX2829_Reset_d, RFD_MAX2829_Reset_d; |
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[1927] | 310 | |
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[2906] | 311 | //Register all outputs to the radios |
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| 312 | wire RFA_TxEn_w; |
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| 313 | wire RFB_TxEn_w; |
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| 314 | wire RFC_TxEn_w; |
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| 315 | wire RFD_TxEn_w; |
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| 316 | wire RFA_RxEn_w; |
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| 317 | wire RFB_RxEn_w; |
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| 318 | wire RFC_RxEn_w; |
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| 319 | wire RFD_RxEn_w; |
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| 320 | wire RFA_RxHP_w; |
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| 321 | wire RFB_RxHP_w; |
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| 322 | wire RFC_RxHP_w; |
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| 323 | wire RFD_RxHP_w; |
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| 324 | wire RFA_SHDN_w; |
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| 325 | wire RFB_SHDN_w; |
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| 326 | wire RFC_SHDN_w; |
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| 327 | wire RFD_SHDN_w; |
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| 328 | wire RFA_PAEn_24_w; |
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| 329 | wire RFB_PAEn_24_w; |
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| 330 | wire RFC_PAEn_24_w; |
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| 331 | wire RFD_PAEn_24_w; |
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| 332 | wire RFA_PAEn_5_w; |
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| 333 | wire RFB_PAEn_5_w; |
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| 334 | wire RFC_PAEn_5_w; |
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| 335 | wire RFD_PAEn_5_w; |
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| 336 | wire [6:0] RFA_B_w; |
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| 337 | wire [6:0] RFB_B_w; |
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| 338 | wire [6:0] RFC_B_w; |
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| 339 | wire [6:0] RFD_B_w; |
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| 340 | wire [1:0] RFA_AntSw_w; |
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| 341 | wire [1:0] RFB_AntSw_w; |
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| 342 | wire [1:0] RFC_AntSw_w; |
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| 343 | wire [1:0] RFD_AntSw_w; |
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[1927] | 344 | |
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[2906] | 345 | always @(posedge Bus2IP_Clk) |
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| 346 | begin |
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| 347 | RFA_TxEn <= RFA_TxEn_w; |
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| 348 | RFB_TxEn <= RFB_TxEn_w; |
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| 349 | RFC_TxEn <= RFC_TxEn_w; |
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| 350 | RFD_TxEn <= RFD_TxEn_w; |
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| 351 | RFA_RxEn <= RFA_RxEn_w; |
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| 352 | RFB_RxEn <= RFB_RxEn_w; |
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| 353 | RFC_RxEn <= RFC_RxEn_w; |
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| 354 | RFD_RxEn <= RFD_RxEn_w; |
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| 355 | RFA_RxHP <= RFA_RxHP_w; |
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| 356 | RFB_RxHP <= RFB_RxHP_w; |
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| 357 | RFC_RxHP <= RFC_RxHP_w; |
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| 358 | RFD_RxHP <= RFD_RxHP_w; |
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| 359 | RFA_SHDN <= RFA_SHDN_w; |
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| 360 | RFB_SHDN <= RFB_SHDN_w; |
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| 361 | RFC_SHDN <= RFC_SHDN_w; |
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| 362 | RFD_SHDN <= RFD_SHDN_w; |
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| 363 | RFA_PAEn_24 <= RFA_PAEn_24_w; |
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| 364 | RFB_PAEn_24 <= RFB_PAEn_24_w; |
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| 365 | RFC_PAEn_24 <= RFC_PAEn_24_w; |
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| 366 | RFD_PAEn_24 <= RFD_PAEn_24_w; |
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| 367 | RFA_PAEn_5 <= RFA_PAEn_5_w; |
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| 368 | RFB_PAEn_5 <= RFB_PAEn_5_w; |
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| 369 | RFC_PAEn_5 <= RFC_PAEn_5_w; |
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| 370 | RFD_PAEn_5 <= RFD_PAEn_5_w; |
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| 371 | |
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| 372 | RFA_B <= RFA_B_w; |
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| 373 | RFB_B <= RFB_B_w; |
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| 374 | RFC_B <= RFC_B_w; |
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| 375 | RFD_B <= RFD_B_w; |
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| 376 | |
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| 377 | RFA_AntSw <= RFA_AntSw_w; |
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| 378 | RFB_AntSw <= RFB_AntSw_w; |
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| 379 | RFC_AntSw <= RFC_AntSw_w; |
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| 380 | RFD_AntSw <= RFD_AntSw_w; |
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| 381 | end |
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| 382 | |
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| 383 | //Register combinational reset signal here for lower fanout |
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| 384 | always @(posedge Bus2IP_Clk) |
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| 385 | begin |
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| 386 | RFA_MAX2829_Reset_d <= RFA_MAX2829_Reset; |
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| 387 | RFB_MAX2829_Reset_d <= RFB_MAX2829_Reset; |
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| 388 | RFC_MAX2829_Reset_d <= RFC_MAX2829_Reset; |
---|
| 389 | RFD_MAX2829_Reset_d <= RFD_MAX2829_Reset; |
---|
| 390 | end |
---|
| 391 | |
---|
[1927] | 392 | // Slave register write process; only implemented for RW and WO registers |
---|
| 393 | always @( posedge Bus2IP_Clk ) |
---|
| 394 | begin |
---|
| 395 | if ( Bus2IP_Resetn == 1'b0 ) |
---|
| 396 | begin |
---|
| 397 | slv_reg0 <= 0; //All zeros on reset- Tx/Rx disabled, SHDN (active low) enabled |
---|
| 398 | slv_reg1 <= `TXTIMING_REG_ON_RESET; |
---|
| 399 | slv_reg2 <= `TXGAINS_REG_ON_RESET; |
---|
| 400 | slv_reg3 <= 0; |
---|
| 401 | slv_reg4 <= `CLKDIV_GAINTIMING_REG_ON_RESET; |
---|
| 402 | slv_reg5 <= 0; |
---|
| 403 | slv_reg6 <= 0; |
---|
| 404 | slv_reg7 <= 0; |
---|
| 405 | slv_reg8 <= 0; |
---|
| 406 | slv_reg9 <= 0; |
---|
| 407 | slv_reg10 <= 0; |
---|
| 408 | end |
---|
| 409 | else |
---|
| 410 | case ( slv_reg_write_sel ) |
---|
| 411 | 11'b10000000000 : |
---|
| 412 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 413 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 414 | slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 415 | 11'b01000000000 : |
---|
| 416 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 417 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 418 | slv_reg1[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 419 | 11'b00100000000 : |
---|
| 420 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 421 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 422 | slv_reg2[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 423 | 11'b00010000000 : |
---|
| 424 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 425 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 426 | slv_reg3[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 427 | 11'b00001000000 : |
---|
| 428 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 429 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 430 | slv_reg4[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 431 | 11'b00000100000 : |
---|
| 432 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 433 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 434 | slv_reg5[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 435 | 11'b00000010000 : |
---|
| 436 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 437 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 438 | slv_reg6[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 439 | 11'b00000001000 : |
---|
| 440 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 441 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 442 | slv_reg7[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 443 | 11'b00000000100 : |
---|
| 444 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 445 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 446 | slv_reg8[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 447 | 11'b00000000010 : |
---|
| 448 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 449 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 450 | slv_reg9[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 451 | 11'b00000000001 : |
---|
| 452 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 453 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 454 | slv_reg10[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
---|
| 455 | |
---|
| 456 | default : begin |
---|
| 457 | slv_reg0 <= slv_reg0; |
---|
| 458 | slv_reg1 <= slv_reg1; |
---|
| 459 | slv_reg2 <= slv_reg2; |
---|
| 460 | slv_reg3 <= slv_reg3; |
---|
| 461 | slv_reg4 <= slv_reg4; |
---|
| 462 | slv_reg5 <= slv_reg5; |
---|
| 463 | slv_reg6 <= slv_reg6; |
---|
| 464 | slv_reg7 <= slv_reg7; |
---|
| 465 | slv_reg8 <= slv_reg8; |
---|
| 466 | slv_reg9 <= slv_reg9; |
---|
| 467 | slv_reg10 <= slv_reg10; |
---|
| 468 | end |
---|
| 469 | endcase |
---|
| 470 | |
---|
| 471 | end // SLAVE_REG_WRITE_PROC |
---|
| 472 | |
---|
| 473 | // Slave model register read mux |
---|
| 474 | // All registers can be read |
---|
| 475 | always @* |
---|
| 476 | begin |
---|
| 477 | case ( slv_reg_read_sel ) |
---|
| 478 | 64'b1000000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg0; |
---|
| 479 | 64'b0100000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg1; |
---|
| 480 | 64'b0010000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg2; |
---|
| 481 | 64'b0001000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg3; |
---|
| 482 | 64'b0000100000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg4; |
---|
| 483 | 64'b0000010000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg5; |
---|
| 484 | 64'b0000001000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg6; |
---|
| 485 | 64'b0000000100000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg7; |
---|
| 486 | 64'b0000000010000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg8; |
---|
| 487 | 64'b0000000001000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg9; |
---|
| 488 | 64'b0000000000100000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg10; |
---|
| 489 | 64'b0000000000010000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= status_reg; |
---|
[2906] | 490 | 64'b0000000000001000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[0]}; |
---|
| 491 | 64'b0000000000000100000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[1]}; |
---|
| 492 | 64'b0000000000000010000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[2]}; |
---|
| 493 | 64'b0000000000000001000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[3]}; |
---|
| 494 | 64'b0000000000000000100000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[4]}; |
---|
| 495 | 64'b0000000000000000010000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[5]}; |
---|
| 496 | 64'b0000000000000000001000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[6]}; |
---|
| 497 | 64'b0000000000000000000100000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[7]}; |
---|
| 498 | 64'b0000000000000000000010000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[8]}; |
---|
| 499 | 64'b0000000000000000000001000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[9]}; |
---|
| 500 | 64'b0000000000000000000000100000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[10]}; |
---|
| 501 | 64'b0000000000000000000000010000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[11]}; |
---|
| 502 | 64'b0000000000000000000000001000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_mirrorReg_data[12]}; |
---|
| 503 | 64'b0000000000000000000000000100000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[0]}; |
---|
| 504 | 64'b0000000000000000000000000010000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[1]}; |
---|
| 505 | 64'b0000000000000000000000000001000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[2]}; |
---|
| 506 | 64'b0000000000000000000000000000100000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[3]}; |
---|
| 507 | 64'b0000000000000000000000000000010000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[4]}; |
---|
| 508 | 64'b0000000000000000000000000000001000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[5]}; |
---|
| 509 | 64'b0000000000000000000000000000000100000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[6]}; |
---|
| 510 | 64'b0000000000000000000000000000000010000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[7]}; |
---|
| 511 | 64'b0000000000000000000000000000000001000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[8]}; |
---|
| 512 | 64'b0000000000000000000000000000000000100000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[9]}; |
---|
| 513 | 64'b0000000000000000000000000000000000010000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[10]}; |
---|
| 514 | 64'b0000000000000000000000000000000000001000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[11]}; |
---|
| 515 | 64'b0000000000000000000000000000000000000100000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_mirrorReg_data[12]}; |
---|
| 516 | 64'b0000000000000000000000000000000000000010000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[0]}; |
---|
| 517 | 64'b0000000000000000000000000000000000000001000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[1]}; |
---|
| 518 | 64'b0000000000000000000000000000000000000000100000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[2]}; |
---|
| 519 | 64'b0000000000000000000000000000000000000000010000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[3]}; |
---|
| 520 | 64'b0000000000000000000000000000000000000000001000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[4]}; |
---|
| 521 | 64'b0000000000000000000000000000000000000000000100000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[5]}; |
---|
| 522 | 64'b0000000000000000000000000000000000000000000010000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[6]}; |
---|
| 523 | 64'b0000000000000000000000000000000000000000000001000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[7]}; |
---|
| 524 | 64'b0000000000000000000000000000000000000000000000100000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[8]}; |
---|
| 525 | 64'b0000000000000000000000000000000000000000000000010000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[9]}; |
---|
| 526 | 64'b0000000000000000000000000000000000000000000000001000000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[10]}; |
---|
| 527 | 64'b0000000000000000000000000000000000000000000000000100000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[11]}; |
---|
| 528 | 64'b0000000000000000000000000000000000000000000000000010000000000000 : slv_ip2bus_data <= {18'b0, RFC_mirrorReg_data[12]}; |
---|
| 529 | 64'b0000000000000000000000000000000000000000000000000001000000000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[0]}; |
---|
| 530 | 64'b0000000000000000000000000000000000000000000000000000100000000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[1]}; |
---|
| 531 | 64'b0000000000000000000000000000000000000000000000000000010000000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[2]}; |
---|
| 532 | 64'b0000000000000000000000000000000000000000000000000000001000000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[3]}; |
---|
| 533 | 64'b0000000000000000000000000000000000000000000000000000000100000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[4]}; |
---|
| 534 | 64'b0000000000000000000000000000000000000000000000000000000010000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[5]}; |
---|
| 535 | 64'b0000000000000000000000000000000000000000000000000000000001000000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[6]}; |
---|
| 536 | 64'b0000000000000000000000000000000000000000000000000000000000100000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[7]}; |
---|
| 537 | 64'b0000000000000000000000000000000000000000000000000000000000010000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[8]}; |
---|
| 538 | 64'b0000000000000000000000000000000000000000000000000000000000001000 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[9]}; |
---|
| 539 | 64'b0000000000000000000000000000000000000000000000000000000000000100 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[10]}; |
---|
| 540 | 64'b0000000000000000000000000000000000000000000000000000000000000010 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[11]}; |
---|
| 541 | 64'b0000000000000000000000000000000000000000000000000000000000000001 : slv_ip2bus_data <= {18'b0, RFD_mirrorReg_data[12]}; default : slv_ip2bus_data <= 0; |
---|
[1927] | 542 | endcase |
---|
| 543 | end // SLAVE_REG_READ_PROC |
---|
| 544 | |
---|
| 545 | /* Address map: |
---|
| 546 | HDL is coded [MSB:LSB] = [31:0], per Xilinx's convention for AXI peripherals |
---|
| 547 | regX[31] maps to 0x80000000 in C driver |
---|
| 548 | regX[ 0] maps to 0x00000001 in C driver |
---|
| 549 | |
---|
| 550 | 0: RW: MAX2829 control signals and control source (sw vs. hw) |
---|
| 551 | Mask for RFA: 0x000000FF |
---|
| 552 | Mask for RFB: 0x0000FF00 |
---|
| 553 | Mask for RFC: 0x00FF0000 |
---|
| 554 | Mask for RFD: 0xFF000000 |
---|
| 555 | [31:28] = RFD Control: {TxEn, RxEn, RxHP, SHDN} 0xF0000000 |
---|
| 556 | [27:24] = RFD Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) 0x0F000000 |
---|
| 557 | [23:20] = RFC Control: {TxEn, RxEn, RxHP, SHDN} 0x00F00000 |
---|
| 558 | [19:16] = RFC Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) 0x000F0000 |
---|
| 559 | [15:12] = RFB Control: {TxEn, RxEn, RxHP, SHDN} 0x0000F000 |
---|
| 560 | [11: 8] = RFB Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) 0x00000F00 |
---|
| 561 | [ 7: 4] = RFA Control: {TxEn, RxEn, RxHP, SHDN} 0x000000F0 |
---|
| 562 | [ 3: 0] = RFA Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) 0x0000000F |
---|
| 563 | |
---|
| 564 | 1: RW: Tx Timing |
---|
| 565 | Shared by all RF interfaces |
---|
| 566 | [31:24] = Delay before Tx VGA ramp start 0xFF000000 |
---|
| 567 | [23:16] = Delay before PA enable 0x00FF0000 |
---|
| 568 | [15: 8] = Delay before MAX2829 TxEn assertion 0x0000FF00 |
---|
| 569 | [ 7: 0] = Delay before usr_startPHY assertion 0x000000FF |
---|
| 570 | |
---|
| 571 | 2: RW: Tx Gains |
---|
| 572 | [ 31] = RF D Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x80000000 |
---|
| 573 | [ 30] = Reserved |
---|
| 574 | [29:24] = RF D Tx Gain 0x3F000000 |
---|
| 575 | [ 23] = RF C Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00800000 |
---|
| 576 | [ 22] = Reserved |
---|
| 577 | [21:16] = RF C Tx Gain 0x003F0000 |
---|
| 578 | [ 15] = RF B Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00008000 |
---|
| 579 | [ 14] = Reserved |
---|
| 580 | [13: 8] = RF B Tx Gain 0x00003F00 |
---|
| 581 | [ 7] = RF A Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00000080 |
---|
| 582 | [ 6] = Reserved |
---|
| 583 | [ 5: 0] = RF A Tx Gain 0x0000003F |
---|
| 584 | |
---|
| 585 | 3: RW: Rx gains |
---|
| 586 | [ 31] = RFD Rx gain ctrl source (0=register values, 1=usr_ ports) 0x80000000 |
---|
| 587 | [30:29] = RFD Rx RF Gain 0x60000000 |
---|
| 588 | [28:24] = RFD Rx BB Gain 0x1F000000 |
---|
| 589 | [ 23] = RFC Rx gain ctrl source (0=register values, 1=usr_ ports) 0x00800000 |
---|
| 590 | [22:21] = RFC Rx RF Gain 0x00600000 |
---|
| 591 | [20:16] = RFC Rx BB Gain 0x001F0000 |
---|
| 592 | [ 15] = RFB Rx gain ctrl source (0=register values, 1=usr_ ports) 0x00008000 |
---|
| 593 | [14:13] = RFB Rx RF Gain 0x00006000 |
---|
| 594 | [12: 8] = RFB Rx BB Gain 0x00001F00 |
---|
| 595 | [ 7] = RFA Rx gain ctrl source (0=register values, 1=usr_ ports) 0x00000080 |
---|
| 596 | [ 6: 5] = RFA Rx RF Gain 0x00000060 |
---|
| 597 | [ 4: 0] = RFA Rx BB Gain 0x0000001F |
---|
| 598 | |
---|
| 599 | 4: RW: Clock dividers & Tx gain ramp config |
---|
| 600 | [31:16] = Reserved 0xFFFF0000 |
---|
| 601 | [15:12] = Tx VGA ramp time step 0x0000F000 |
---|
| 602 | [11: 8] = Tx VGA ramp gain step 0x00000F00 |
---|
| 603 | [ 7] = Reserved 0x00000080 |
---|
| 604 | [ 6: 4] = SPI clock divider 0x00000070 |
---|
| 605 | [ 3: 2] = Reserved 0x0000000C |
---|
| 606 | [ 1: 0] = TxTiming clock divider 0x00000003 |
---|
| 607 | |
---|
| 608 | 5: WO: SPI write register |
---|
| 609 | Special register: |
---|
| 610 | * Write from software triggers SPI transaction |
---|
| 611 | * IPIF WrACK delayed until SPI is done (i.e. software doesn't have to poll; Xil_Out32 blocks until SPI is done) |
---|
| 612 | * Reads of this register return last SPI word transferred by software (might be stale, if usr_ SPI ports are also used) |
---|
| 613 | [31:28] SPI chip select mask RF[D:A] 0x80000000=RFD, 0x40000000=RFC, 0x20000000=RFB, 0x10000000=RFA |
---|
| 614 | [27:20] Reserved 0x0FF00000 |
---|
| 615 | [19:16] Register address to write 0x000F0000 |
---|
| 616 | [15:14] Reserved 0x0000C000 |
---|
| 617 | [13: 0] Register value to write 0x00003FFF |
---|
| 618 | |
---|
| 619 | |
---|
| 620 | |
---|
| 621 | 6 to 10: Reserved (RW 32-bit registers implemented; no connection to external hardware) |
---|
| 622 | |
---|
| 623 | 11: RO: Status bits |
---|
| 624 | Same per-RF masks as reg[0], same control signal masks as reg[0] |
---|
| 625 | [31:28] = RFD control status {TxEn, RxEn, RxHP, SHDN} |
---|
| 626 | [ 27] = RFD MAX2829 PLL locked (1=locked) |
---|
| 627 | [ 26] = RFD SPI transfer in progress |
---|
| 628 | [25:24] = {RFD PA_2 ON, RFD PA_5 ON} |
---|
| 629 | |
---|
| 630 | [23:20] = RFC control status {TxEn, RxEn, RxHP, SHDN} |
---|
| 631 | [ 19] = RFC MAX2829 PLL locked (1=locked) |
---|
| 632 | [ 18] = RFC SPI transfer in progress |
---|
| 633 | [17:16] = {RFC PA_2 ON, RFC PA_5 ON} |
---|
| 634 | |
---|
| 635 | [15:12] = RFB control status {TxEn, RxEn, RxHP, SHDN} |
---|
| 636 | [ 11] = RFB MAX2829 PLL locked (1=locked) |
---|
| 637 | [ 10] = RFB SPI transfer in progress |
---|
| 638 | [ 9: 8] = {RFB PA_2 ON, RFB PA_5 ON} |
---|
| 639 | |
---|
| 640 | [ 7: 4] = RFA control status {TxEn, RxEn, RxHP, SHDN} |
---|
| 641 | [ 3] = RFA MAX2829 PLL locked (1=locked) |
---|
| 642 | [ 2] = RFA SPI transfer in progress |
---|
| 643 | [ 1: 0] = {RFA PA_2 ON, RFA PA_5 ON} |
---|
| 644 | |
---|
| 645 | 12 to 63: RO: Read-only registers which mirror state of MAX2829 internal registers (since MAX2829 SPI is write-only) |
---|
| 646 | * Registers are initialized (on FPGA config and MAX2829 reset) to MAX2829 defaults, to match MAX2829 reset state |
---|
| 647 | * Register values are updated automatically by SPI writes (via reg4 or via usr_ SPI port use) |
---|
| 648 | * Every register is: |
---|
| 649 | [31:14] Reserved; returns 0 on read |
---|
| 650 | [13: 0] Register value (14 bits) |
---|
| 651 | |
---|
| 652 | 12...24: RO: Local copies of MAX2829 registers for RFA |
---|
| 653 | 12: RFA MAX2829 reg0 |
---|
| 654 | ... |
---|
| 655 | 24: RFA MAX2829 regC |
---|
| 656 | |
---|
| 657 | 25...37: RO: Local copies of MAX2829 registers for RFB |
---|
| 658 | 25: RFB MAX2829 reg0 |
---|
| 659 | ... |
---|
| 660 | 37: RFB MAX2829 regC |
---|
| 661 | |
---|
| 662 | 38...50: RO: Local copies of MAX2829 registers for RFC |
---|
| 663 | 38: RFC MAX2829 reg0 |
---|
| 664 | ... |
---|
| 665 | 50: RFC MAX2829 regC |
---|
| 666 | |
---|
| 667 | 51...63: RO: Local copies of MAX2829 registers for RFD |
---|
| 668 | 51: RFD MAX2829 reg0 |
---|
| 669 | ... |
---|
| 670 | 63: RFD MAX2829 regC |
---|
| 671 | |
---|
| 672 | */ |
---|
| 673 | |
---|
| 674 | //Only regs 0 to 10 can be written; 12 to 63 are RO |
---|
| 675 | assign slv_reg_write_sel = Bus2IP_WrCE[63:53]; //WrCE[63:0] maps to slv_reg[0:63] |
---|
| 676 | |
---|
| 677 | //All regs can be read; ACK all reads immediately |
---|
| 678 | assign slv_reg_read_sel = Bus2IP_RdCE[63:0]; |
---|
| 679 | assign slv_read_ack = |Bus2IP_RdCE[63:0]; |
---|
| 680 | |
---|
| 681 | //Write ack for reg5 (WrCE[58]) is delayed by SPI transfer |
---|
| 682 | // All other regs ACK writes immediately |
---|
| 683 | assign slv_write_ack_normalRegisters = |{Bus2IP_WrCE[63:59], Bus2IP_WrCE[57:53]}; |
---|
| 684 | |
---|
| 685 | assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data : 0 ; |
---|
| 686 | assign IP2Bus_RdAck = slv_read_ack; |
---|
| 687 | assign IP2Bus_Error = 0; |
---|
| 688 | |
---|
| 689 | //spi_tx_reg_write (Bus2IP_WrCE[58]) de-asserts as soon as transaction is ACK'd |
---|
| 690 | // so this mux switches back to the generic ACK as soon as the SPI xfer is done |
---|
| 691 | //Thus, the duration of assertion for spi_xfer_done doesn't really matter |
---|
| 692 | //A bit fast-n-loose, but works ok |
---|
| 693 | assign IP2Bus_WrAck = spi_tx_reg_write ? spi_xfer_done : slv_write_ack_normalRegisters; |
---|
| 694 | |
---|
| 695 | //Register 0: MAX2829 control |
---|
| 696 | assign {RFD_TxEn_sw, RFD_RxEn_sw, RFD_RxHP_sw, RFD_SHDN_sw} = slv_reg0[31:28]; |
---|
| 697 | assign {RFD_TxEn_ctrlSrc, RFD_RxEn_ctrlSrc, RFD_RxHP_ctrlSrc, RFD_SHDN_ctrlSrc} = slv_reg0[27:24]; |
---|
| 698 | |
---|
| 699 | assign {RFC_TxEn_sw, RFC_RxEn_sw, RFC_RxHP_sw, RFC_SHDN_sw} = slv_reg0[23:20]; |
---|
| 700 | assign {RFC_TxEn_ctrlSrc, RFC_RxEn_ctrlSrc, RFC_RxHP_ctrlSrc, RFC_SHDN_ctrlSrc} = slv_reg0[19:16]; |
---|
| 701 | |
---|
| 702 | assign {RFB_TxEn_sw, RFB_RxEn_sw, RFB_RxHP_sw, RFB_SHDN_sw} = slv_reg0[15:12]; |
---|
| 703 | assign {RFB_TxEn_ctrlSrc, RFB_RxEn_ctrlSrc, RFB_RxHP_ctrlSrc, RFB_SHDN_ctrlSrc} = slv_reg0[11:8]; |
---|
| 704 | |
---|
| 705 | assign {RFA_TxEn_sw, RFA_RxEn_sw, RFA_RxHP_sw, RFA_SHDN_sw} = slv_reg0[7:4]; |
---|
| 706 | assign {RFA_TxEn_ctrlSrc, RFA_RxEn_ctrlSrc, RFA_RxHP_ctrlSrc, RFA_SHDN_ctrlSrc} = slv_reg0[3:0]; |
---|
| 707 | |
---|
| 708 | |
---|
| 709 | //Register 1: Tx timing |
---|
| 710 | assign TxTiming_dly_TxGainRamp = slv_reg1[31:24]; |
---|
| 711 | assign TxTiming_dly_PowerAmpEn = slv_reg1[23:16]; |
---|
| 712 | assign TxTiming_dly_TxEn = slv_reg1[15: 8]; |
---|
| 713 | assign TxTiming_dly_startPHY = slv_reg1[ 7: 0]; |
---|
| 714 | |
---|
| 715 | //Register 2: Tx gains |
---|
| 716 | assign RFD_TxGain_sw = slv_reg2[29:24]; |
---|
| 717 | assign RFC_TxGain_sw = slv_reg2[21:16]; |
---|
| 718 | assign RFB_TxGain_sw = slv_reg2[13: 8]; |
---|
| 719 | assign RFA_TxGain_sw = slv_reg2[ 5: 0]; |
---|
| 720 | |
---|
| 721 | assign RFD_TxGain_ctrlSrc = slv_reg2[31]; |
---|
| 722 | assign RFC_TxGain_ctrlSrc = slv_reg2[23]; |
---|
| 723 | assign RFB_TxGain_ctrlSrc = slv_reg2[15]; |
---|
| 724 | assign RFA_TxGain_ctrlSrc = slv_reg2[ 7]; |
---|
| 725 | |
---|
| 726 | //Register 3: Rx gains |
---|
| 727 | assign RFD_RxGainBB_sw = slv_reg3[28:24]; |
---|
| 728 | assign RFC_RxGainBB_sw = slv_reg3[20:16]; |
---|
| 729 | assign RFB_RxGainBB_sw = slv_reg3[12: 8]; |
---|
| 730 | assign RFA_RxGainBB_sw = slv_reg3[ 4: 0]; |
---|
| 731 | |
---|
| 732 | assign RFD_RxGainRF_sw = slv_reg3[30:29]; |
---|
| 733 | assign RFC_RxGainRF_sw = slv_reg3[22:21]; |
---|
| 734 | assign RFB_RxGainRF_sw = slv_reg3[14:13]; |
---|
| 735 | assign RFA_RxGainRF_sw = slv_reg3[ 6: 5]; |
---|
| 736 | |
---|
| 737 | assign RFD_RxGain_ctrlSrc = slv_reg3[31]; |
---|
| 738 | assign RFC_RxGain_ctrlSrc = slv_reg3[23]; |
---|
| 739 | assign RFB_RxGain_ctrlSrc = slv_reg3[15]; |
---|
| 740 | assign RFA_RxGain_ctrlSrc = slv_reg3[ 7]; |
---|
| 741 | |
---|
| 742 | //Register 4: Clock dividers & Tx gain ramp config |
---|
| 743 | assign TxGainRamp_timeStep = slv_reg4[15:12]; |
---|
| 744 | assign TxGainRamp_gainStep = slv_reg4[11: 8]; |
---|
| 745 | assign spi_clk_div_sel = slv_reg4[ 6: 4]; |
---|
| 746 | assign txTiming_clk_div_sel = slv_reg4[ 1: 0]; |
---|
| 747 | |
---|
| 748 | //Register 5: SPI write |
---|
| 749 | assign spi_rfsel_mask_sw = slv_reg5[31:28]; |
---|
| 750 | assign spi_tx_regaddr = slv_reg5[19:16]; |
---|
| 751 | assign spi_tx_regdata = slv_reg5[13: 0]; |
---|
| 752 | |
---|
| 753 | //Use the IPIF write-enable for the SPI Tx register as the SPI go |
---|
| 754 | // The bus will be paused until the SPI transfer is finished |
---|
| 755 | assign spi_tx_reg_write = Bus2IP_WrCE[58]; |
---|
| 756 | |
---|
| 757 | //Register 11: Read-only status bits |
---|
| 758 | assign status_reg[31:28] = {RFD_TxEn, RFD_RxEn, RFD_RxHP, RFD_SHDN}; |
---|
| 759 | assign status_reg[27:24] = {RFD_LD, ~RFD_SPI_CSn, RFD_PAEn_24, RFD_PAEn_5}; |
---|
| 760 | |
---|
| 761 | assign status_reg[23:20] = {RFC_TxEn, RFC_RxEn, RFC_RxHP, RFC_SHDN}; |
---|
| 762 | assign status_reg[19:16] = {RFC_LD, ~RFC_SPI_CSn, RFC_PAEn_24, RFC_PAEn_5}; |
---|
| 763 | |
---|
| 764 | assign status_reg[15:12] = {RFB_TxEn, RFB_RxEn, RFB_RxHP, RFB_SHDN}; |
---|
| 765 | assign status_reg[11: 8] = {RFB_LD, ~RFB_SPI_CSn, RFB_PAEn_24, RFB_PAEn_5}; |
---|
| 766 | |
---|
| 767 | assign status_reg[ 7: 4] = {RFA_TxEn, RFA_RxEn, RFA_RxHP, RFA_SHDN}; |
---|
| 768 | assign status_reg[ 3: 0] = {RFA_LD, ~RFA_SPI_CSn, RFA_PAEn_24, RFA_PAEn_5}; |
---|
| 769 | |
---|
| 770 | //Mux the various control signals between software and hardware control |
---|
| 771 | assign RFA_txStart = RFA_TxEn_ctrlSrc ? usr_RFA_TxEn : RFA_TxEn_sw; |
---|
| 772 | assign RFB_txStart = RFB_TxEn_ctrlSrc ? usr_RFB_TxEn : RFB_TxEn_sw; |
---|
| 773 | assign RFC_txStart = RFC_TxEn_ctrlSrc ? usr_RFC_TxEn : RFC_TxEn_sw; |
---|
| 774 | assign RFD_txStart = RFD_TxEn_ctrlSrc ? usr_RFD_TxEn : RFD_TxEn_sw; |
---|
| 775 | |
---|
[2906] | 776 | assign RFA_RxEn_w = RFA_RxEn_ctrlSrc ? usr_RFA_RxEn : RFA_RxEn_sw; |
---|
| 777 | assign RFB_RxEn_w = RFB_RxEn_ctrlSrc ? usr_RFB_RxEn : RFB_RxEn_sw; |
---|
| 778 | assign RFC_RxEn_w = RFC_RxEn_ctrlSrc ? usr_RFC_RxEn : RFC_RxEn_sw; |
---|
| 779 | assign RFD_RxEn_w = RFD_RxEn_ctrlSrc ? usr_RFD_RxEn : RFD_RxEn_sw; |
---|
[1927] | 780 | |
---|
[2906] | 781 | assign RFA_RxHP_w = RFA_RxHP_ctrlSrc ? usr_RFA_RxHP : RFA_RxHP_sw; |
---|
| 782 | assign RFB_RxHP_w = RFB_RxHP_ctrlSrc ? usr_RFB_RxHP : RFB_RxHP_sw; |
---|
| 783 | assign RFC_RxHP_w = RFC_RxHP_ctrlSrc ? usr_RFC_RxHP : RFC_RxHP_sw; |
---|
| 784 | assign RFD_RxHP_w = RFD_RxHP_ctrlSrc ? usr_RFD_RxHP : RFD_RxHP_sw; |
---|
[1927] | 785 | |
---|
[2906] | 786 | assign RFA_SHDN_w = RFA_SHDN_ctrlSrc ? usr_RFA_SHDN : RFA_SHDN_sw; |
---|
| 787 | assign RFB_SHDN_w = RFB_SHDN_ctrlSrc ? usr_RFB_SHDN : RFB_SHDN_sw; |
---|
| 788 | assign RFC_SHDN_w = RFC_SHDN_ctrlSrc ? usr_RFC_SHDN : RFC_SHDN_sw; |
---|
| 789 | assign RFD_SHDN_w = RFD_SHDN_ctrlSrc ? usr_RFD_SHDN : RFD_SHDN_sw; |
---|
[1927] | 790 | |
---|
| 791 | assign RFA_TxGain_target = RFA_TxGain_ctrlSrc ? usr_RFA_TxGain : RFA_TxGain_sw; |
---|
| 792 | assign RFB_TxGain_target = RFB_TxGain_ctrlSrc ? usr_RFB_TxGain : RFB_TxGain_sw; |
---|
| 793 | assign RFC_TxGain_target = RFC_TxGain_ctrlSrc ? usr_RFC_TxGain : RFC_TxGain_sw; |
---|
| 794 | assign RFD_TxGain_target = RFD_TxGain_ctrlSrc ? usr_RFD_TxGain : RFD_TxGain_sw; |
---|
| 795 | |
---|
| 796 | assign RFA_RxGainBB = RFA_RxGain_ctrlSrc ? usr_RFA_RxGainBB : RFA_RxGainBB_sw; |
---|
| 797 | assign RFB_RxGainBB = RFB_RxGain_ctrlSrc ? usr_RFB_RxGainBB : RFB_RxGainBB_sw; |
---|
| 798 | assign RFC_RxGainBB = RFC_RxGain_ctrlSrc ? usr_RFC_RxGainBB : RFC_RxGainBB_sw; |
---|
| 799 | assign RFD_RxGainBB = RFD_RxGain_ctrlSrc ? usr_RFD_RxGainBB : RFD_RxGainBB_sw; |
---|
| 800 | |
---|
| 801 | assign RFA_RxGainRF = RFA_RxGain_ctrlSrc ? usr_RFA_RxGainRF : RFA_RxGainRF_sw; |
---|
| 802 | assign RFB_RxGainRF = RFB_RxGain_ctrlSrc ? usr_RFB_RxGainRF : RFB_RxGainRF_sw; |
---|
| 803 | assign RFC_RxGainRF = RFC_RxGain_ctrlSrc ? usr_RFC_RxGainRF : RFC_RxGainRF_sw; |
---|
| 804 | assign RFD_RxGainRF = RFD_RxGain_ctrlSrc ? usr_RFD_RxGainRF : RFD_RxGainRF_sw; |
---|
| 805 | |
---|
| 806 | |
---|
| 807 | //Output OR'd PHYStart signal (most PHYs use this, so any TxEnable will start the PHY) |
---|
| 808 | // Individual PHYStarts are provided in case user has multiple PHYs connected to different RF paths |
---|
| 809 | assign usr_any_PHYStart = usr_RFA_PHYStart || usr_RFB_PHYStart || usr_RFC_PHYStart || usr_RFD_PHYStart; |
---|
| 810 | |
---|
| 811 | //SKY13370 needs 100-250nsec to settle, so make the switch as soon as we know Tx process is starting |
---|
| 812 | //2-bit control signal in hardware, but only two valid states: |
---|
| 813 | // [V1 V2] = [1 0] => Rx path connected to SMA, Tx path terminated to 50 ohms (PA must be off!) |
---|
| 814 | // [V1 V2] = [0 1] => Tx path connected to SMA, Rx path terminated to 50 ohms |
---|
| 815 | //RFx_AntSw[0] = SKY13370.V1, RFx_AntSw[1] = SKY13370.V2 |
---|
[2906] | 816 | assign RFA_AntSw_w[1:0] = {~RFA_txStart, RFA_txStart}; |
---|
| 817 | assign RFB_AntSw_w[1:0] = {~RFB_txStart, RFB_txStart}; |
---|
| 818 | assign RFC_AntSw_w[1:0] = {~RFC_txStart, RFC_txStart}; |
---|
| 819 | assign RFD_AntSw_w[1:0] = {~RFD_txStart, RFD_txStart}; |
---|
[1927] | 820 | |
---|
| 821 | //PAs are enabled by single wire per band |
---|
| 822 | // One path's 2.4 and 5GHz PAs should never be enabled simultaneously |
---|
| 823 | //2.4GHz PA is on when: |
---|
| 824 | // TxTiming state machine asserts PAEn AND |
---|
| 825 | // MAX2829.reg5[0] == 0 (indicating MAX2829 is tuned to 2.4GHz band) |
---|
| 826 | //5GHz PA is on when: |
---|
| 827 | // TxTiming state machine asserts PAEn AND |
---|
| 828 | // MAX2829.reg5[0] == 1 (indicating MAX2829 is tuned to 5GHz band) |
---|
| 829 | //RFx_MAX2829_mirrorRegs are indexed [MSB:LSB]=[13:0] to match other busses in this core, |
---|
| 830 | // so the LSB (bit [0] in MAX2829 datasheet) is RFA_MAX2829_mirrorRegs[x][0] here |
---|
[2906] | 831 | assign RFA_PAEn_24_w = (RFA_PAEn & ~(RFA_mirrorReg_data[5][0])); |
---|
| 832 | assign RFB_PAEn_24_w = (RFB_PAEn & ~(RFB_mirrorReg_data[5][0])); |
---|
| 833 | assign RFC_PAEn_24_w = (RFC_PAEn & ~(RFC_mirrorReg_data[5][0])); |
---|
| 834 | assign RFD_PAEn_24_w = (RFD_PAEn & ~(RFD_mirrorReg_data[5][0])); |
---|
[1927] | 835 | |
---|
[2906] | 836 | assign RFA_PAEn_5_w = (RFA_PAEn & (RFA_mirrorReg_data[5][0])); |
---|
| 837 | assign RFB_PAEn_5_w = (RFB_PAEn & (RFB_mirrorReg_data[5][0])); |
---|
| 838 | assign RFC_PAEn_5_w = (RFC_PAEn & (RFC_mirrorReg_data[5][0])); |
---|
| 839 | assign RFD_PAEn_5_w = (RFD_PAEn & (RFD_mirrorReg_data[5][0])); |
---|
[1927] | 840 | |
---|
| 841 | //MAX2829 gain control bus |
---|
| 842 | // radio_controller.RFx_B[6:0] maps to MAX2829.B[7:1] |
---|
| 843 | // radio_controller.RFx_B[6] is MSB, radio_controller.RFx_B[0] is LSB |
---|
| 844 | // MAX2829.B7 is MSB, MAX2829.B1 is LSB |
---|
| 845 | //When SPI gain control is disabled: |
---|
| 846 | // In Tx mode: |
---|
| 847 | // MAX2829.B[7] is don't care |
---|
| 848 | // MAX2829.B[6:1] = Tx RF VGA (6'd63 is max gain, 6'd0 is min gain (approx max-30dB)) |
---|
| 849 | // In Rx mode: |
---|
| 850 | // MAX2829.B[7:6] = Rx RF LNA (2'd3 is max gain (30dB), 2'd1 is min gain (0dB), 2'd0 is invalid) |
---|
| 851 | // MAX2829.B[5:1] = Rx BB VGA (5'd31 is max gain (approx 62dB), 5'd0 is min gain (approx 0dB) |
---|
| 852 | //assign RFA_B = RFA_txStart ? {1'b0, RFA_TxGain_ramped} : {RFA_RxGainRF, RFA_RxGainBB}; |
---|
| 853 | //assign RFB_B = RFB_txStart ? {1'b0, RFB_TxGain_ramped} : {RFB_RxGainRF, RFB_RxGainBB}; |
---|
| 854 | //assign RFC_B = RFC_txStart ? {1'b0, RFC_TxGain_ramped} : {RFC_RxGainRF, RFC_RxGainBB}; |
---|
| 855 | //assign RFD_B = RFD_txStart ? {1'b0, RFD_TxGain_ramped} : {RFD_RxGainRF, RFD_RxGainBB}; |
---|
[2906] | 856 | assign {RFA_B_w[0], RFA_B_w[1], RFA_B_w[2], RFA_B_w[3], RFA_B_w[4], RFA_B_w[5], RFA_B_w[6]} = RFA_txStart ? {1'b0, RFA_TxGain_ramped} : {RFA_RxGainRF, RFA_RxGainBB}; |
---|
| 857 | assign {RFB_B_w[0], RFB_B_w[1], RFB_B_w[2], RFB_B_w[3], RFB_B_w[4], RFB_B_w[5], RFB_B_w[6]} = RFB_txStart ? {1'b0, RFB_TxGain_ramped} : {RFB_RxGainRF, RFB_RxGainBB}; |
---|
| 858 | assign {RFC_B_w[0], RFC_B_w[1], RFC_B_w[2], RFC_B_w[3], RFC_B_w[4], RFC_B_w[5], RFC_B_w[6]} = RFC_txStart ? {1'b0, RFC_TxGain_ramped} : {RFC_RxGainRF, RFC_RxGainBB}; |
---|
| 859 | assign {RFD_B_w[0], RFD_B_w[1], RFD_B_w[2], RFD_B_w[3], RFD_B_w[4], RFD_B_w[5], RFD_B_w[6]} = RFD_txStart ? {1'b0, RFD_TxGain_ramped} : {RFD_RxGainRF, RFD_RxGainBB}; |
---|
[1927] | 860 | |
---|
| 861 | //Simple state machines for fixed timing of Tx events (MAX2829 TxEn, PA enable and PHY start) |
---|
| 862 | // One per RF path, to handle case of user designs which do Tx/Rx asychronously across paths |
---|
| 863 | // All use same timing values, as these are really tuned to the hardware, not the Tx signal |
---|
| 864 | radio_controller_TxTiming RFA_txTiming ( |
---|
| 865 | .clk(Bus2IP_Clk), |
---|
| 866 | .reset(~Bus2IP_Resetn),//.reset is active high, IPIF Resetn is active low |
---|
| 867 | |
---|
| 868 | .clk_div(txTiming_clk_div_sel), |
---|
| 869 | |
---|
| 870 | .sw_start(RFA_txStart), |
---|
| 871 | |
---|
| 872 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
| 873 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
| 874 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
| 875 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
| 876 | |
---|
| 877 | .gainRamp_TxGainTarget(RFA_TxGain_target), |
---|
| 878 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
| 879 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
| 880 | .gainRamp_TxGainOut(RFA_TxGain_ramped), |
---|
| 881 | |
---|
[2906] | 882 | .TxEn(RFA_TxEn_w), |
---|
[1927] | 883 | .PAEn(RFA_PAEn), |
---|
| 884 | .PHYStart(usr_RFA_PHYStart) |
---|
| 885 | ); |
---|
| 886 | radio_controller_TxTiming RFB_txTiming ( |
---|
| 887 | .clk(Bus2IP_Clk), |
---|
| 888 | .reset(~Bus2IP_Resetn),//.reset is active high, IPIF Resetn is active low |
---|
| 889 | |
---|
| 890 | .clk_div(txTiming_clk_div_sel), |
---|
| 891 | |
---|
| 892 | .sw_start(RFB_txStart), |
---|
| 893 | |
---|
| 894 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
| 895 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
| 896 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
| 897 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
| 898 | |
---|
| 899 | .gainRamp_TxGainTarget(RFB_TxGain_target), |
---|
| 900 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
| 901 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
| 902 | .gainRamp_TxGainOut(RFB_TxGain_ramped), |
---|
| 903 | |
---|
[2906] | 904 | .TxEn(RFB_TxEn_w), |
---|
[1927] | 905 | .PAEn(RFB_PAEn), |
---|
| 906 | .PHYStart(usr_RFB_PHYStart) |
---|
| 907 | ); |
---|
| 908 | radio_controller_TxTiming RFC_txTiming ( |
---|
| 909 | .clk(Bus2IP_Clk), |
---|
| 910 | .reset(~Bus2IP_Resetn),//.reset is active high, IPIF Resetn is active low |
---|
| 911 | |
---|
| 912 | .clk_div(txTiming_clk_div_sel), |
---|
| 913 | |
---|
| 914 | .sw_start(RFC_txStart), |
---|
| 915 | |
---|
| 916 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
| 917 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
| 918 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
| 919 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
| 920 | |
---|
| 921 | .gainRamp_TxGainTarget(RFC_TxGain_target), |
---|
| 922 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
| 923 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
| 924 | .gainRamp_TxGainOut(RFC_TxGain_ramped), |
---|
| 925 | |
---|
[2906] | 926 | .TxEn(RFC_TxEn_w), |
---|
[1927] | 927 | .PAEn(RFC_PAEn), |
---|
| 928 | .PHYStart(usr_RFC_PHYStart) |
---|
| 929 | ); |
---|
| 930 | radio_controller_TxTiming RFD_txTiming ( |
---|
| 931 | .clk(Bus2IP_Clk), |
---|
| 932 | .reset(~Bus2IP_Resetn),//.reset is active high, IPIF Resetn is active low |
---|
| 933 | |
---|
| 934 | .clk_div(txTiming_clk_div_sel), |
---|
| 935 | |
---|
| 936 | .sw_start(RFD_txStart), |
---|
| 937 | |
---|
| 938 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
| 939 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
| 940 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
| 941 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
| 942 | |
---|
| 943 | .gainRamp_TxGainTarget(RFD_TxGain_target), |
---|
| 944 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
| 945 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
| 946 | .gainRamp_TxGainOut(RFD_TxGain_ramped), |
---|
| 947 | |
---|
[2906] | 948 | .TxEn(RFD_TxEn_w), |
---|
[1927] | 949 | .PAEn(RFD_PAEn), |
---|
| 950 | .PHYStart(usr_RFD_PHYStart) |
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| 951 | ); |
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| 952 | |
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| 953 | //Signals to detect when MAX2829 hardware reset occurs (TxEn=1, RxEn=1, SHDN=0) |
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| 954 | // Reset can be triggered by hardware or software, depending on the user config |
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| 955 | assign RFA_MAX2829_Reset = (RFA_TxEn & RFA_RxEn & ~RFA_SHDN); |
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| 956 | assign RFB_MAX2829_Reset = (RFB_TxEn & RFB_RxEn & ~RFB_SHDN); |
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| 957 | assign RFC_MAX2829_Reset = (RFC_TxEn & RFC_RxEn & ~RFC_SHDN); |
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| 958 | assign RFD_MAX2829_Reset = (RFD_TxEn & RFD_RxEn & ~RFD_SHDN); |
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| 959 | |
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| 960 | //Use a counter to generate a blinking error signal to indicate a radio in standby that hasn't yet locked |
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| 961 | reg [23:0] error_blink_counter = 24'b0; |
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| 962 | always @(posedge Bus2IP_Clk) |
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[2906] | 963 | begin |
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[1927] | 964 | error_blink_counter <= error_blink_counter + 1; |
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[2906] | 965 | |
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| 966 | usr_RFA_statLED_Tx <= RFA_SHDN_w ? (RFA_TxEn_w | ((~RFA_LD) & error_blink_counter[23])) : 1'b0; |
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| 967 | usr_RFA_statLED_Rx <= RFA_SHDN_w ? (RFA_RxEn_w | ((~RFA_LD) & error_blink_counter[23])) : 1'b0;; |
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[1927] | 968 | |
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[2906] | 969 | usr_RFB_statLED_Tx <= RFB_SHDN_w ? (RFB_TxEn_w | ((~RFB_LD) & error_blink_counter[23])) : 1'b0; |
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| 970 | usr_RFB_statLED_Rx <= RFB_SHDN_w ? (RFB_RxEn_w | ((~RFB_LD) & error_blink_counter[23])) : 1'b0;; |
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[1927] | 971 | |
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[2906] | 972 | usr_RFC_statLED_Tx <= RFC_SHDN_w ? (RFC_TxEn_w | ((~RFC_LD) & error_blink_counter[23])) : 1'b0; |
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| 973 | usr_RFC_statLED_Rx <= RFC_SHDN_w ? (RFC_RxEn_w | ((~RFC_LD) & error_blink_counter[23])) : 1'b0;; |
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[1927] | 974 | |
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[2906] | 975 | usr_RFD_statLED_Tx <= RFD_SHDN_w ? (RFD_TxEn_w | ((~RFD_LD) & error_blink_counter[23])) : 1'b0; |
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| 976 | usr_RFD_statLED_Rx <= RFD_SHDN_w ? (RFD_RxEn_w | ((~RFD_LD) & error_blink_counter[23])) : 1'b0;; |
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| 977 | end |
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[1927] | 978 | |
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| 979 | //Mask per-RF path to enable SPI transactions |
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| 980 | // Driven by register for software control, usr_ port for hardware control |
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| 981 | assign spi_rfsel_mask = usr_SPI_ctrlSrc ? usr_SPI_rfsel : spi_rfsel_mask_sw; |
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| 982 | |
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[2906] | 983 | wire RFA_reg_write_en; |
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| 984 | wire RFB_reg_write_en; |
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| 985 | wire RFC_reg_write_en; |
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| 986 | wire RFD_reg_write_en; |
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[1927] | 987 | |
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[2906] | 988 | assign RFA_reg_write_en = ((spi_rfsel_mask & 4'b0001) != 0); |
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| 989 | assign RFB_reg_write_en = ((spi_rfsel_mask & 4'b0010) != 0); |
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| 990 | assign RFC_reg_write_en = ((spi_rfsel_mask & 4'b0100) != 0); |
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| 991 | assign RFD_reg_write_en = ((spi_rfsel_mask & 4'b1000) != 0); |
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| 992 | |
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| 993 | radio_mirror_regs RFA_mirror_regs ( |
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| 994 | .clk(Bus2IP_Clk), |
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| 995 | .reset(RFA_MAX2829_Reset_d), |
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| 996 | .spi_reg_wr_data(spi_tx_regdata), |
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| 997 | .spi_reg_wr_addr(spi_tx_regaddr), |
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| 998 | .spi_reg_wr_en(RFA_reg_write_en), |
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| 999 | .mirror_reg0(RFA_mirrorReg_data[0]), |
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| 1000 | .mirror_reg1(RFA_mirrorReg_data[1]), |
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| 1001 | .mirror_reg2(RFA_mirrorReg_data[2]), |
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| 1002 | .mirror_reg3(RFA_mirrorReg_data[3]), |
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| 1003 | .mirror_reg4(RFA_mirrorReg_data[4]), |
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| 1004 | .mirror_reg5(RFA_mirrorReg_data[5]), |
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| 1005 | .mirror_reg6(RFA_mirrorReg_data[6]), |
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| 1006 | .mirror_reg7(RFA_mirrorReg_data[7]), |
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| 1007 | .mirror_reg8(RFA_mirrorReg_data[8]), |
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| 1008 | .mirror_reg9(RFA_mirrorReg_data[9]), |
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| 1009 | .mirror_regA(RFA_mirrorReg_data[10]), |
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| 1010 | .mirror_regB(RFA_mirrorReg_data[11]), |
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| 1011 | .mirror_regC(RFA_mirrorReg_data[12]) |
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| 1012 | ); |
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[1927] | 1013 | |
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[2906] | 1014 | radio_mirror_regs RFB_mirror_regs ( |
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| 1015 | .clk(Bus2IP_Clk), |
---|
| 1016 | .reset(RFB_MAX2829_Reset_d), |
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| 1017 | .spi_reg_wr_data(spi_tx_regdata), |
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| 1018 | .spi_reg_wr_addr(spi_tx_regaddr), |
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| 1019 | .spi_reg_wr_en(RFB_reg_write_en), |
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| 1020 | .mirror_reg0(RFB_mirrorReg_data[0]), |
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| 1021 | .mirror_reg1(RFB_mirrorReg_data[1]), |
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| 1022 | .mirror_reg2(RFB_mirrorReg_data[2]), |
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| 1023 | .mirror_reg3(RFB_mirrorReg_data[3]), |
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| 1024 | .mirror_reg4(RFB_mirrorReg_data[4]), |
---|
| 1025 | .mirror_reg5(RFB_mirrorReg_data[5]), |
---|
| 1026 | .mirror_reg6(RFB_mirrorReg_data[6]), |
---|
| 1027 | .mirror_reg7(RFB_mirrorReg_data[7]), |
---|
| 1028 | .mirror_reg8(RFB_mirrorReg_data[8]), |
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| 1029 | .mirror_reg9(RFB_mirrorReg_data[9]), |
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| 1030 | .mirror_regA(RFB_mirrorReg_data[10]), |
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| 1031 | .mirror_regB(RFB_mirrorReg_data[11]), |
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| 1032 | .mirror_regC(RFB_mirrorReg_data[12]) |
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| 1033 | ); |
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[1927] | 1034 | |
---|
[2906] | 1035 | radio_mirror_regs RFC_mirror_regs ( |
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| 1036 | .clk(Bus2IP_Clk), |
---|
| 1037 | .reset(RFC_MAX2829_Reset_d), |
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| 1038 | .spi_reg_wr_data(spi_tx_regdata), |
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| 1039 | .spi_reg_wr_addr(spi_tx_regaddr), |
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| 1040 | .spi_reg_wr_en(RFC_reg_write_en), |
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| 1041 | .mirror_reg0(RFC_mirrorReg_data[0]), |
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| 1042 | .mirror_reg1(RFC_mirrorReg_data[1]), |
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| 1043 | .mirror_reg2(RFC_mirrorReg_data[2]), |
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| 1044 | .mirror_reg3(RFC_mirrorReg_data[3]), |
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| 1045 | .mirror_reg4(RFC_mirrorReg_data[4]), |
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| 1046 | .mirror_reg5(RFC_mirrorReg_data[5]), |
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| 1047 | .mirror_reg6(RFC_mirrorReg_data[6]), |
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| 1048 | .mirror_reg7(RFC_mirrorReg_data[7]), |
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| 1049 | .mirror_reg8(RFC_mirrorReg_data[8]), |
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| 1050 | .mirror_reg9(RFC_mirrorReg_data[9]), |
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| 1051 | .mirror_regA(RFC_mirrorReg_data[10]), |
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| 1052 | .mirror_regB(RFC_mirrorReg_data[11]), |
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| 1053 | .mirror_regC(RFC_mirrorReg_data[12]) |
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| 1054 | ); |
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[1927] | 1055 | |
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[2906] | 1056 | radio_mirror_regs RFD_mirror_regs ( |
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| 1057 | .clk(Bus2IP_Clk), |
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| 1058 | .reset(RFD_MAX2829_Reset_d), |
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| 1059 | .spi_reg_wr_data(spi_tx_regdata), |
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| 1060 | .spi_reg_wr_addr(spi_tx_regaddr), |
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| 1061 | .spi_reg_wr_en(RFD_reg_write_en), |
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| 1062 | .mirror_reg0(RFD_mirrorReg_data[0]), |
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| 1063 | .mirror_reg1(RFD_mirrorReg_data[1]), |
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| 1064 | .mirror_reg2(RFD_mirrorReg_data[2]), |
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| 1065 | .mirror_reg3(RFD_mirrorReg_data[3]), |
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| 1066 | .mirror_reg4(RFD_mirrorReg_data[4]), |
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| 1067 | .mirror_reg5(RFD_mirrorReg_data[5]), |
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| 1068 | .mirror_reg6(RFD_mirrorReg_data[6]), |
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| 1069 | .mirror_reg7(RFD_mirrorReg_data[7]), |
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| 1070 | .mirror_reg8(RFD_mirrorReg_data[8]), |
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| 1071 | .mirror_reg9(RFD_mirrorReg_data[9]), |
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| 1072 | .mirror_regA(RFD_mirrorReg_data[10]), |
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| 1073 | .mirror_regB(RFD_mirrorReg_data[11]), |
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| 1074 | .mirror_regC(RFD_mirrorReg_data[12]) |
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| 1075 | ); |
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| 1076 | |
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[1927] | 1077 | //MAX2829 CS is active-low; warp_spi_io.spi_cs is active high |
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| 1078 | assign RFA_SPI_CSn = ~(spi_rfsel_mask[0] & spi_cs); |
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| 1079 | assign RFB_SPI_CSn = ~(spi_rfsel_mask[1] & spi_cs); |
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| 1080 | assign RFC_SPI_CSn = ~(spi_rfsel_mask[2] & spi_cs); |
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| 1081 | assign RFD_SPI_CSn = ~(spi_rfsel_mask[3] & spi_cs); |
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| 1082 | |
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| 1083 | assign RFA_SPI_MOSI = spi_mosi; |
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| 1084 | assign RFB_SPI_MOSI = spi_mosi; |
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| 1085 | assign RFC_SPI_MOSI = spi_mosi; |
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| 1086 | assign RFD_SPI_MOSI = spi_mosi; |
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| 1087 | |
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| 1088 | //Mask each SCLK output by the corresponding CS |
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| 1089 | // No point toggling SCLKs that will be ignored |
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| 1090 | assign RFA_SPI_SCLK = (spi_sclk & spi_rfsel_mask[0]); |
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| 1091 | assign RFB_SPI_SCLK = (spi_sclk & spi_rfsel_mask[1]); |
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| 1092 | assign RFC_SPI_SCLK = (spi_sclk & spi_rfsel_mask[2]); |
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| 1093 | assign RFD_SPI_SCLK = (spi_sclk & spi_rfsel_mask[3]); |
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| 1094 | |
---|
| 1095 | //MAX2829 SPI uses 18-bit transfers, formatted as {regData[13:0] regAddr[3:0]}, data and addr both transfer MSB first |
---|
| 1096 | wire [17:0] spi_tx_data_word; |
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| 1097 | assign spi_tx_data_word[17:0] = usr_SPI_ctrlSrc ? {usr_SPI_regdata, usr_SPI_regaddr} : {spi_tx_regdata, spi_tx_regaddr}; |
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| 1098 | |
---|
| 1099 | assign spi_go = usr_SPI_ctrlSrc ? usr_SPI_go : spi_tx_reg_write; |
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| 1100 | |
---|
| 1101 | assign usr_SPI_active = spi_cs; |
---|
| 1102 | |
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| 1103 | warp_spi_io #(.SPI_XFER_LEN(18)) spi_io ( |
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| 1104 | .sys_clk(Bus2IP_Clk), |
---|
| 1105 | .reset(~Bus2IP_Resetn),//reset input is active high, IPIF resetn is active low |
---|
| 1106 | .go(spi_go), |
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| 1107 | .done(spi_xfer_done), |
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| 1108 | .clkDiv(spi_clk_div_sel), |
---|
| 1109 | |
---|
| 1110 | .currBitNum(), |
---|
| 1111 | |
---|
| 1112 | .txData({14'b0, spi_tx_data_word}), |
---|
| 1113 | |
---|
| 1114 | .rxData1(), |
---|
| 1115 | .rxData2(), |
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| 1116 | .rxData3(), |
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| 1117 | .rxData4(), |
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| 1118 | |
---|
| 1119 | .spi_cs(spi_cs), |
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| 1120 | .spi_sclk(spi_sclk), |
---|
| 1121 | |
---|
| 1122 | .spi_mosi(spi_mosi), |
---|
| 1123 | |
---|
| 1124 | .spi_miso1(1'b0), |
---|
| 1125 | .spi_miso2(1'b0), |
---|
| 1126 | .spi_miso3(1'b0), |
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| 1127 | .spi_miso4(1'b0) |
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| 1128 | ); |
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| 1129 | |
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| 1130 | endmodule |
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