[889] | 1 | BEGIN radio_controller
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| 2 |
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| 3 | ## Peripheral Options
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| 4 | OPTION IPTYPE = PERIPHERAL
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| 5 | OPTION IMP_NETLIST = TRUE
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| 6 | OPTION HDL = MIXED
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| 7 | OPTION IP_GROUP = MICROBLAZE:PPC:USER
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| 8 | OPTION DESC = "WARP Radio Controller (PLB46)"
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| 9 | OPTION USAGE_LEVEL = BASE_USER #Enable this core in base system builder
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| 10 |
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[1700] | 11 | IO_INTERFACE IO_IF = radio_controller_ports, IO_TYPE = WARP_RADIOCONTROLLER_V1
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[889] | 12 |
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| 13 | ## Bus Interfaces
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| 14 | BUS_INTERFACE BUS = SPLB, BUS_TYPE = SLAVE, BUS_STD = PLBV46
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[1711] | 15 | BUS_INTERFACE BUS = RC2RB_RAD1, BUS_STD = WARP_RC2RB_V1, BUS_TYPE = INITIATOR
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| 16 | BUS_INTERFACE BUS = RC2RB_RAD2, BUS_STD = WARP_RC2RB_V1, BUS_TYPE = INITIATOR
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| 17 | BUS_INTERFACE BUS = RC2RB_RAD3, BUS_STD = WARP_RC2RB_V1, BUS_TYPE = INITIATOR
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| 18 | BUS_INTERFACE BUS = RC2RB_RAD4, BUS_STD = WARP_RC2RB_V1, BUS_TYPE = INITIATOR
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[889] | 19 |
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| 20 | ## Generics for VHDL or Parameters for Verilog
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| 21 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, BUS = SPLB, ADDRESS = BASE, PAIR = C_HIGHADDR
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| 22 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SPLB, ADDRESS = HIGH, PAIR = C_BASEADDR
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| 23 | PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
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| 24 | PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
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| 25 | PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
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| 26 | PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
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| 27 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
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| 28 | PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
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| 29 | PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
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| 30 | PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
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| 31 | PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
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| 32 | PARAMETER C_FAMILY = virtex4, DT = STRING
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| 33 |
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| 34 | ## Ports
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| 35 | PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
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| 36 | PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
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| 37 | PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
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| 38 | PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
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| 39 | PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
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| 40 | PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
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| 41 | PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
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| 42 | PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
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| 43 | PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
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| 44 | PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
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| 45 | PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
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| 46 | PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
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| 47 | PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
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| 48 | PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
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| 49 | PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
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| 50 | PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
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| 51 | PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
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| 52 | PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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| 53 | PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
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| 54 | PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
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| 55 | PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
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| 56 | PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
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| 57 | PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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| 58 | PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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| 59 | PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
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| 60 | PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
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| 61 | PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
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| 62 | PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
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| 63 | PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
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| 64 | PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
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| 65 | PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
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| 66 | PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
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| 67 | PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
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| 68 | PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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| 69 | PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
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| 70 | PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
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| 71 | PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
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| 72 | PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
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| 73 | PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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| 74 | PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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| 75 | PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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| 76 | PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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| 77 |
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| 78 |
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[1700] | 79 | #Copy of PLB clock, driven out to radio_bridges
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| 80 | # (which need the clock to stay synchronous with the radio_controller, but aren't otherwise attached to the PLB)
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[1711] | 81 | PORT controller_logic_clk1 = "controller_logic_clk", DIR = O, BUS = RC2RB_RAD1
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| 82 | PORT controller_logic_clk2 = "controller_logic_clk", DIR = O, BUS = RC2RB_RAD2
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| 83 | PORT controller_logic_clk3 = "controller_logic_clk", DIR = O, BUS = RC2RB_RAD3
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| 84 | PORT controller_logic_clk4 = "controller_logic_clk", DIR = O, BUS = RC2RB_RAD4
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[1061] | 85 |
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[1700] | 86 | #SPI clock and data outputs, shared by all radio_bridges
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[1711] | 87 | PORT spi_clk1 = "controller_spi_clk", DIR = O, BUS = RC2RB_RAD1
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| 88 | PORT spi_clk2 = "controller_spi_clk", DIR = O, BUS = RC2RB_RAD2
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| 89 | PORT spi_clk3 = "controller_spi_clk", DIR = O, BUS = RC2RB_RAD3
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| 90 | PORT spi_clk4 = "controller_spi_clk", DIR = O, BUS = RC2RB_RAD4
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[1061] | 91 |
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[1711] | 92 | PORT data_out1 = "controller_spi_data", DIR = O, BUS = RC2RB_RAD1
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| 93 | PORT data_out2 = "controller_spi_data", DIR = O, BUS = RC2RB_RAD2
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| 94 | PORT data_out3 = "controller_spi_data", DIR = O, BUS = RC2RB_RAD3
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| 95 | PORT data_out4 = "controller_spi_data", DIR = O, BUS = RC2RB_RAD4
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[1061] | 96 |
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[1711] | 97 | PORT radio1_cs = "controller_radio_cs", DIR = O, BUS = RC2RB_RAD1
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| 98 | PORT dac1_cs = "controller_dac_cs", DIR = O, BUS = RC2RB_RAD1
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| 99 | PORT radio1_SHDN = "controller_SHDN", DIR = O, BUS = RC2RB_RAD1
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| 100 | PORT radio1_TxEn = "controller_TxEn", DIR = O, BUS = RC2RB_RAD1
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| 101 | PORT radio1_RxEn = "controller_RxEn", DIR = O, BUS = RC2RB_RAD1
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| 102 | PORT radio1_RxHP = "controller_RxHP", DIR = O, BUS = RC2RB_RAD1
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| 103 | PORT radio1_24PA = "controller_24PA", DIR = O, BUS = RC2RB_RAD1
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| 104 | PORT radio1_5PA = "controller_5PA", DIR = O, BUS = RC2RB_RAD1
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| 105 | PORT radio1_ANTSW = "controller_ANTSW", DIR = O, VEC = [0:1], BUS = RC2RB_RAD1
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| 106 | PORT radio1_LED = "controller_LED", DIR = O, VEC = [0:2], BUS = RC2RB_RAD1
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| 107 | PORT radio1_ADC_RX_DCS = "controller_RX_ADC_DCS", DIR = O, BUS = RC2RB_RAD1
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| 108 | PORT radio1_ADC_RX_DFS = "controller_RX_ADC_DFS", DIR = O, BUS = RC2RB_RAD1
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| 109 | PORT radio1_ADC_RX_OTRA = "controller_RX_ADC_OTRA", DIR = I, BUS = RC2RB_RAD1
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| 110 | PORT radio1_ADC_RX_OTRB = "controller_RX_ADC_OTRB", DIR = I, BUS = RC2RB_RAD1
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| 111 | PORT radio1_ADC_RX_PWDNA = "controller_RX_ADC_PWDNA", DIR = O, BUS = RC2RB_RAD1
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| 112 | PORT radio1_ADC_RX_PWDNB = "controller_RX_ADC_PWDNB", DIR = O, BUS = RC2RB_RAD1
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| 113 | PORT radio1_DIPSW = "controller_DIPSW", DIR = I, VEC = [0:3], BUS = RC2RB_RAD1
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| 114 | PORT radio1_RSSI_ADC_CLAMP = "controller_RSSI_ADC_CLAMP", DIR = O, BUS = RC2RB_RAD1
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| 115 | PORT radio1_RSSI_ADC_HIZ = "controller_RSSI_ADC_HIZ", DIR = O, BUS = RC2RB_RAD1
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| 116 | PORT radio1_RSSI_ADC_OTR = "controller_RSSI_ADC_OTR", DIR = I, BUS = RC2RB_RAD1
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| 117 | PORT radio1_RSSI_ADC_SLEEP = "controller_RSSI_ADC_SLEEP", DIR = O, BUS = RC2RB_RAD1
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| 118 | PORT radio1_RSSI_ADC_D = "controller_RSSI_ADC_D", DIR = I, VEC = [0:9], BUS = RC2RB_RAD1
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| 119 | PORT radio1_LD = "controller_LD", DIR = I, BUS = RC2RB_RAD1
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| 120 | PORT radio1_TX_DAC_PLL_LOCK = "controller_DAC_PLL_LOCK", DIR = I, BUS = RC2RB_RAD1
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| 121 | PORT radio1_TX_DAC_RESET = "controller_DAC_RESET", DIR = O, BUS = RC2RB_RAD1
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| 122 | PORT radio1_SHDN_external = "controller_SHDN_external", DIR = I, BUS = RC2RB_RAD1
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| 123 | PORT radio1_TxEn_external = "controller_TxEn_external", DIR = I, BUS = RC2RB_RAD1
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| 124 | PORT radio1_RxEn_external = "controller_RxEn_external", DIR = I, BUS = RC2RB_RAD1
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| 125 | PORT radio1_RxHP_external = "controller_RxHP_external", DIR = I, BUS = RC2RB_RAD1
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| 126 | PORT radio1_TxStart = "controller_TxStart", DIR = O, BUS = RC2RB_RAD1
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| 127 | PORT radio1_TxGain = "controller_Tx_gain", DIR = O, VEC = [0:5], BUS = RC2RB_RAD1
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| 128 |
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[1705] | 129 | PORT radio2_cs = "controller_radio_cs", DIR = O, BUS = RC2RB_RAD2
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| 130 | PORT dac2_cs = "controller_dac_cs", DIR = O, BUS = RC2RB_RAD2
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| 131 | PORT radio2_SHDN = "controller_SHDN", DIR = O, BUS = RC2RB_RAD2
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| 132 | PORT radio2_TxEn = "controller_TxEn", DIR = O, BUS = RC2RB_RAD2
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| 133 | PORT radio2_RxEn = "controller_RxEn", DIR = O, BUS = RC2RB_RAD2
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| 134 | PORT radio2_RxHP = "controller_RxHP", DIR = O, BUS = RC2RB_RAD2
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| 135 | PORT radio2_24PA = "controller_24PA", DIR = O, BUS = RC2RB_RAD2
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| 136 | PORT radio2_5PA = "controller_5PA", DIR = O, BUS = RC2RB_RAD2
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| 137 | PORT radio2_ANTSW = "controller_ANTSW", DIR = O, VEC = [0:1], BUS = RC2RB_RAD2
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| 138 | PORT radio2_LED = "controller_LED", DIR = O, VEC = [0:2], BUS = RC2RB_RAD2
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| 139 | PORT radio2_ADC_RX_DCS = "controller_RX_ADC_DCS", DIR = O, BUS = RC2RB_RAD2
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| 140 | PORT radio2_ADC_RX_DFS = "controller_RX_ADC_DFS", DIR = O, BUS = RC2RB_RAD2
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| 141 | PORT radio2_ADC_RX_OTRA = "controller_RX_ADC_OTRA", DIR = I, BUS = RC2RB_RAD2
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| 142 | PORT radio2_ADC_RX_OTRB = "controller_RX_ADC_OTRB", DIR = I, BUS = RC2RB_RAD2
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| 143 | PORT radio2_ADC_RX_PWDNA = "controller_RX_ADC_PWDNA", DIR = O, BUS = RC2RB_RAD2
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| 144 | PORT radio2_ADC_RX_PWDNB = "controller_RX_ADC_PWDNB", DIR = O, BUS = RC2RB_RAD2
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| 145 | PORT radio2_DIPSW = "controller_DIPSW", DIR = I, VEC = [0:3], BUS = RC2RB_RAD2
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| 146 | PORT radio2_RSSI_ADC_CLAMP = "controller_RSSI_ADC_CLAMP", DIR = O, BUS = RC2RB_RAD2
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| 147 | PORT radio2_RSSI_ADC_HIZ = "controller_RSSI_ADC_HIZ", DIR = O, BUS = RC2RB_RAD2
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| 148 | PORT radio2_RSSI_ADC_OTR = "controller_RSSI_ADC_OTR", DIR = I, BUS = RC2RB_RAD2
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| 149 | PORT radio2_RSSI_ADC_SLEEP = "controller_RSSI_ADC_SLEEP", DIR = O, BUS = RC2RB_RAD2
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| 150 | PORT radio2_RSSI_ADC_D = "controller_RSSI_ADC_D", DIR = I, VEC = [0:9], BUS = RC2RB_RAD2
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| 151 | PORT radio2_LD = "controller_LD", DIR = I, BUS = RC2RB_RAD2
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| 152 | PORT radio2_TX_DAC_PLL_LOCK = "controller_DAC_PLL_LOCK", DIR = I, BUS = RC2RB_RAD2
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| 153 | PORT radio2_TX_DAC_RESET = "controller_DAC_RESET", DIR = O, BUS = RC2RB_RAD2
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| 154 | PORT radio2_SHDN_external = "controller_SHDN_external", DIR = I, BUS = RC2RB_RAD2
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| 155 | PORT radio2_TxEn_external = "controller_TxEn_external", DIR = I, BUS = RC2RB_RAD2
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| 156 | PORT radio2_RxEn_external = "controller_RxEn_external", DIR = I, BUS = RC2RB_RAD2
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| 157 | PORT radio2_RxHP_external = "controller_RxHP_external", DIR = I, BUS = RC2RB_RAD2
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| 158 | PORT radio2_TxStart = "controller_TxStart", DIR = O, BUS = RC2RB_RAD2
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| 159 | PORT radio2_TxGain = "controller_Tx_gain", DIR = O, VEC = [0:5], BUS = RC2RB_RAD2
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[1061] | 160 |
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[1711] | 161 | PORT radio3_cs = "controller_radio_cs", DIR = O, BUS = RC2RB_RAD3
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| 162 | PORT dac3_cs = "controller_dac_cs", DIR = O, BUS = RC2RB_RAD3
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| 163 | PORT radio3_SHDN = "controller_SHDN", DIR = O, BUS = RC2RB_RAD3
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| 164 | PORT radio3_TxEn = "controller_TxEn", DIR = O, BUS = RC2RB_RAD3
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| 165 | PORT radio3_RxEn = "controller_RxEn", DIR = O, BUS = RC2RB_RAD3
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| 166 | PORT radio3_RxHP = "controller_RxHP", DIR = O, BUS = RC2RB_RAD3
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| 167 | PORT radio3_24PA = "controller_24PA", DIR = O, BUS = RC2RB_RAD3
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| 168 | PORT radio3_5PA = "controller_5PA", DIR = O, BUS = RC2RB_RAD3
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| 169 | PORT radio3_ANTSW = "controller_ANTSW", DIR = O, VEC = [0:1], BUS = RC2RB_RAD3
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| 170 | PORT radio3_LED = "controller_LED", DIR = O, VEC = [0:2], BUS = RC2RB_RAD3
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| 171 | PORT radio3_ADC_RX_DCS = "controller_RX_ADC_DCS", DIR = O, BUS = RC2RB_RAD3
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| 172 | PORT radio3_ADC_RX_DFS = "controller_RX_ADC_DFS", DIR = O, BUS = RC2RB_RAD3
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| 173 | PORT radio3_ADC_RX_OTRA = "controller_RX_ADC_OTRA", DIR = I, BUS = RC2RB_RAD3
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| 174 | PORT radio3_ADC_RX_OTRB = "controller_RX_ADC_OTRB", DIR = I, BUS = RC2RB_RAD3
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| 175 | PORT radio3_ADC_RX_PWDNA = "controller_RX_ADC_PWDNA", DIR = O, BUS = RC2RB_RAD3
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| 176 | PORT radio3_ADC_RX_PWDNB = "controller_RX_ADC_PWDNB", DIR = O, BUS = RC2RB_RAD3
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| 177 | PORT radio3_DIPSW = "controller_DIPSW", DIR = I, VEC = [0:3], BUS = RC2RB_RAD3
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| 178 | PORT radio3_RSSI_ADC_CLAMP = "controller_RSSI_ADC_CLAMP", DIR = O, BUS = RC2RB_RAD3
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| 179 | PORT radio3_RSSI_ADC_HIZ = "controller_RSSI_ADC_HIZ", DIR = O, BUS = RC2RB_RAD3
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| 180 | PORT radio3_RSSI_ADC_OTR = "controller_RSSI_ADC_OTR", DIR = I, BUS = RC2RB_RAD3
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| 181 | PORT radio3_RSSI_ADC_SLEEP = "controller_RSSI_ADC_SLEEP", DIR = O, BUS = RC2RB_RAD3
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| 182 | PORT radio3_RSSI_ADC_D = "controller_RSSI_ADC_D", DIR = I, VEC = [0:9], BUS = RC2RB_RAD3
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| 183 | PORT radio3_LD = "controller_LD", DIR = I, BUS = RC2RB_RAD3
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| 184 | PORT radio3_TX_DAC_PLL_LOCK = "controller_DAC_PLL_LOCK", DIR = I, BUS = RC2RB_RAD3
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| 185 | PORT radio3_TX_DAC_RESET = "controller_DAC_RESET", DIR = O, BUS = RC2RB_RAD3
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| 186 | PORT radio3_SHDN_external = "controller_SHDN_external", DIR = I, BUS = RC2RB_RAD3
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| 187 | PORT radio3_TxEn_external = "controller_TxEn_external", DIR = I, BUS = RC2RB_RAD3
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| 188 | PORT radio3_RxEn_external = "controller_RxEn_external", DIR = I, BUS = RC2RB_RAD3
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| 189 | PORT radio3_RxHP_external = "controller_RxHP_external", DIR = I, BUS = RC2RB_RAD3
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| 190 | PORT radio3_TxStart = "controller_TxStart", DIR = O, BUS = RC2RB_RAD3
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| 191 | PORT radio3_TxGain = "controller_Tx_gain", DIR = O, VEC = [0:5], BUS = RC2RB_RAD3
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[889] | 192 |
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[1711] | 193 | PORT radio4_cs = "controller_radio_cs", DIR = O, BUS = RC2RB_RAD4
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| 194 | PORT dac4_cs = "controller_dac_cs", DIR = O, BUS = RC2RB_RAD4
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| 195 | PORT radio4_SHDN = "controller_SHDN", DIR = O, BUS = RC2RB_RAD4
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| 196 | PORT radio4_TxEn = "controller_TxEn", DIR = O, BUS = RC2RB_RAD4
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| 197 | PORT radio4_RxEn = "controller_RxEn", DIR = O, BUS = RC2RB_RAD4
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| 198 | PORT radio4_RxHP = "controller_RxHP", DIR = O, BUS = RC2RB_RAD4
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| 199 | PORT radio4_24PA = "controller_24PA", DIR = O, BUS = RC2RB_RAD4
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| 200 | PORT radio4_5PA = "controller_5PA", DIR = O, BUS = RC2RB_RAD4
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| 201 | PORT radio4_ANTSW = "controller_ANTSW", DIR = O, VEC = [0:1], BUS = RC2RB_RAD4
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| 202 | PORT radio4_LED = "controller_LED", DIR = O, VEC = [0:2], BUS = RC2RB_RAD4
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| 203 | PORT radio4_ADC_RX_DCS = "controller_RX_ADC_DCS", DIR = O, BUS = RC2RB_RAD4
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| 204 | PORT radio4_ADC_RX_DFS = "controller_RX_ADC_DFS", DIR = O, BUS = RC2RB_RAD4
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| 205 | PORT radio4_ADC_RX_OTRA = "controller_RX_ADC_OTRA", DIR = I, BUS = RC2RB_RAD4
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| 206 | PORT radio4_ADC_RX_OTRB = "controller_RX_ADC_OTRB", DIR = I, BUS = RC2RB_RAD4
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| 207 | PORT radio4_ADC_RX_PWDNA = "controller_RX_ADC_PWDNA", DIR = O, BUS = RC2RB_RAD4
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| 208 | PORT radio4_ADC_RX_PWDNB = "controller_RX_ADC_PWDNB", DIR = O, BUS = RC2RB_RAD4
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| 209 | PORT radio4_DIPSW = "controller_DIPSW", DIR = I, VEC = [0:3], BUS = RC2RB_RAD4
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| 210 | PORT radio4_RSSI_ADC_CLAMP = "controller_RSSI_ADC_CLAMP", DIR = O, BUS = RC2RB_RAD4
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| 211 | PORT radio4_RSSI_ADC_HIZ = "controller_RSSI_ADC_HIZ", DIR = O, BUS = RC2RB_RAD4
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| 212 | PORT radio4_RSSI_ADC_OTR = "controller_RSSI_ADC_OTR", DIR = I, BUS = RC2RB_RAD4
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| 213 | PORT radio4_RSSI_ADC_SLEEP = "controller_RSSI_ADC_SLEEP", DIR = O, BUS = RC2RB_RAD4
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| 214 | PORT radio4_RSSI_ADC_D = "controller_RSSI_ADC_D", DIR = I, VEC = [0:9], BUS = RC2RB_RAD4
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| 215 | PORT radio4_LD = "controller_LD", DIR = I, BUS = RC2RB_RAD4
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| 216 | PORT radio4_TX_DAC_PLL_LOCK = "controller_DAC_PLL_LOCK", DIR = I, BUS = RC2RB_RAD4
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| 217 | PORT radio4_TX_DAC_RESET = "controller_DAC_RESET", DIR = O, BUS = RC2RB_RAD4
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| 218 | PORT radio4_SHDN_external = "controller_SHDN_external", DIR = I, BUS = RC2RB_RAD4
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| 219 | PORT radio4_TxEn_external = "controller_TxEn_external", DIR = I, BUS = RC2RB_RAD4
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| 220 | PORT radio4_RxEn_external = "controller_RxEn_external", DIR = I, BUS = RC2RB_RAD4
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| 221 | PORT radio4_RxHP_external = "controller_RxHP_external", DIR = I, BUS = RC2RB_RAD4
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| 222 | PORT radio4_TxStart = "controller_TxStart", DIR = O, BUS = RC2RB_RAD4
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| 223 | PORT radio4_TxGain = "controller_Tx_gain", DIR = O, VEC = [0:5], BUS = RC2RB_RAD4
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[1700] | 224 |
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[889] | 225 | END
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