source: PlatformSupport/CustomPeripherals/pcores/radio_controller_v2_00_a/data/radio_controller_v2_1_0.mpd

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##
## Name     : radio_controller
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN radio_controller

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION DESC = RADIO_CONTROLLER
OPTION ARCH_SUPPORT_MAP = (virtex4=DEVELOPMENT)

IO_INTERFACE IO_IF = HW_Ports_RFA, IO_TYPE = W2_RADIOCONTROLLER_V0
IO_INTERFACE IO_IF = HW_Ports_RFB, IO_TYPE = W2_RADIOCONTROLLER_V0
IO_INTERFACE IO_IF = HW_Ports_RFC, IO_TYPE = W2_RADIOCONTROLLER_V0
IO_INTERFACE IO_IF = HW_Ports_RFD, IO_TYPE = W2_RADIOCONTROLLER_V0

IO_INTERFACE IO_IF = USER_Ports_RFA, IO_TYPE = W2_RADIOCONTROLLER_V0
IO_INTERFACE IO_IF = USER_Ports_RFB, IO_TYPE = W2_RADIOCONTROLLER_V0
IO_INTERFACE IO_IF = USER_Ports_RFC, IO_TYPE = W2_RADIOCONTROLLER_V0
IO_INTERFACE IO_IF = USER_Ports_RFD, IO_TYPE = W2_RADIOCONTROLLER_V0

IO_INTERFACE IO_IF = USER_Ports_Misc, IO_TYPE = W2_RADIOCONTROLLER_V0

## Bus Interfaces
BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
PARAMETER C_INCLUDE_DPHASE_TIMER = 0, DT = INTEGER, RANGE = (0, 1)
PARAMETER C_FAMILY = virtex4, DT = STRING

## Ports
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB

PORT RFA_TxEn = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=TxEn
PORT RFB_TxEn = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=TxEn
PORT RFC_TxEn = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=TxEn
PORT RFD_TxEn = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=TxEn

PORT RFA_RxEn = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=RxEn
PORT RFB_RxEn = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=RxEn
PORT RFC_RxEn = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=RxEn
PORT RFD_RxEn = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=RxEn

PORT RFA_RxHP = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=RxHP
PORT RFB_RxHP = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=RxHP
PORT RFC_RxHP = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=RxHP
PORT RFD_RxHP = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=RxHP

PORT RFA_SHDN = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=SHDN
PORT RFB_SHDN = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=SHDN
PORT RFC_SHDN = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=SHDN
PORT RFD_SHDN = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=SHDN

PORT RFA_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=SPI_SCLK
PORT RFB_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=SPI_SCLK
PORT RFC_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=SPI_SCLK
PORT RFD_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=SPI_SCLK

PORT RFA_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=SPI_MOSI
PORT RFB_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=SPI_MOSI
PORT RFC_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=SPI_MOSI
PORT RFD_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=SPI_MOSI

PORT RFA_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=SPI_CSn
PORT RFB_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=SPI_CSn
PORT RFC_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=SPI_CSn
PORT RFD_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=SPI_CSn

PORT RFA_B = "", DIR = O, VEC = [0:6], IO_IF=HW_Ports_RFA, IO_IS=B
PORT RFB_B = "", DIR = O, VEC = [0:6], IO_IF=HW_Ports_RFB, IO_IS=B
PORT RFC_B = "", DIR = O, VEC = [0:6], IO_IF=HW_Ports_RFC, IO_IS=B
PORT RFD_B = "", DIR = O, VEC = [0:6], IO_IF=HW_Ports_RFD, IO_IS=B

PORT RFA_LD = "", DIR = I, IO_IF=HW_Ports_RFA, IO_IS=LD
PORT RFB_LD = "", DIR = I, IO_IF=HW_Ports_RFB, IO_IS=LD
PORT RFC_LD = "", DIR = I, IO_IF=HW_Ports_RFC, IO_IS=LD
PORT RFD_LD = "", DIR = I, IO_IF=HW_Ports_RFD, IO_IS=LD

PORT RFA_PAEn_24 = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=PAEn_24
PORT RFB_PAEn_24 = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=PAEn_24
PORT RFC_PAEn_24 = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=PAEn_24
PORT RFD_PAEn_24 = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=PAEn_24

PORT RFA_PAEn_5 = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=PAEn_5
PORT RFB_PAEn_5 = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=PAEn_5
PORT RFC_PAEn_5 = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=PAEn_5
PORT RFD_PAEn_5 = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=PAEn_5

PORT RFA_AntSw = "", DIR = O, VEC = [0:1], IO_IF=HW_Ports_RFA, IO_IS=AntSw
PORT RFB_AntSw = "", DIR = O, VEC = [0:1], IO_IF=HW_Ports_RFB, IO_IS=AntSw
PORT RFC_AntSw = "", DIR = O, VEC = [0:1], IO_IF=HW_Ports_RFC, IO_IS=AntSw
PORT RFD_AntSw = "", DIR = O, VEC = [0:1], IO_IF=HW_Ports_RFD, IO_IS=AntSw

PORT RFA_DIPSW = "", DIR = I, VEC = [0:3], IO_IF=HW_Ports_RFA, IO_IS=DIPSW
PORT RFB_DIPSW = "", DIR = I, VEC = [0:3], IO_IF=HW_Ports_RFB, IO_IS=DIPSW
PORT RFC_DIPSW = "", DIR = I, VEC = [0:3], IO_IF=HW_Ports_RFC, IO_IS=DIPSW
PORT RFD_DIPSW = "", DIR = I, VEC = [0:3], IO_IF=HW_Ports_RFD, IO_IS=DIPSW

PORT RFA_RX_ADC_DCS = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=ADC_DCS
PORT RFB_RX_ADC_DCS = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=ADC_DCS
PORT RFC_RX_ADC_DCS = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=ADC_DCS
PORT RFD_RX_ADC_DCS = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=ADC_DCS

PORT RFA_RX_ADC_DFS = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=ADC_DFS
PORT RFB_RX_ADC_DFS = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=ADC_DFS
PORT RFC_RX_ADC_DFS = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=ADC_DFS
PORT RFD_RX_ADC_DFS = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=ADC_DFS

PORT RFA_RX_ADC_PWDN = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=ADC_PWDN
PORT RFB_RX_ADC_PWDN = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=ADC_PWDN
PORT RFC_RX_ADC_PWDN = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=ADC_PWDN
PORT RFD_RX_ADC_PWDN = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=ADC_PWDN

PORT RFA_RSSI_ADC_CLAMP = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=RSSI_ADC_RSSI_ADC_CLAMP
PORT RFB_RSSI_ADC_CLAMP = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=RSSI_ADC_RSSI_ADC_CLAMP
PORT RFC_RSSI_ADC_CLAMP = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=RSSI_ADC_RSSI_ADC_CLAMP
PORT RFD_RSSI_ADC_CLAMP = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=RSSI_ADC_RSSI_ADC_CLAMP

PORT RFA_RSSI_ADC_HIZ = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=RSSI_ADC_RSSI_ADC_HIZ
PORT RFB_RSSI_ADC_HIZ = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=RSSI_ADC_RSSI_ADC_HIZ
PORT RFC_RSSI_ADC_HIZ = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=RSSI_ADC_RSSI_ADC_HIZ
PORT RFD_RSSI_ADC_HIZ = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=RSSI_ADC_RSSI_ADC_HIZ

PORT RFA_RSSI_ADC_SLEEP = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=RSSI_ADC_RSSI_ADC_SLEEP
PORT RFB_RSSI_ADC_SLEEP = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=RSSI_ADC_RSSI_ADC_SLEEP
PORT RFC_RSSI_ADC_SLEEP = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=RSSI_ADC_RSSI_ADC_SLEEP
PORT RFD_RSSI_ADC_SLEEP = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=RSSI_ADC_RSSI_ADC_SLEEP

#DAC control ports (integrated into this radio controller, not a separate ad_controller core)
PORT RFA_DAC_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=DAC_SPI_CSn
PORT RFB_DAC_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=DAC_SPI_CSn
PORT RFC_DAC_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=DAC_SPI_CSn
PORT RFD_DAC_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=DAC_SPI_CSn

PORT RFA_DAC_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=DAC_SPI_SCLK
PORT RFB_DAC_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=DAC_SPI_SCLK
PORT RFC_DAC_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=DAC_SPI_SCLK
PORT RFD_DAC_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=DAC_SPI_SCLK

PORT RFA_DAC_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=DAC_SPI_MOSI
PORT RFB_DAC_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=DAC_SPI_MOSI
PORT RFC_DAC_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=DAC_SPI_MOSI
PORT RFD_DAC_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=DAC_SPI_MOSI

PORT RFA_DAC_SPI_MISO = "", DIR = I, IO_IF=HW_Ports_RFA, IO_IS=DAC_SPI_MISO
PORT RFB_DAC_SPI_MISO = "", DIR = I, IO_IF=HW_Ports_RFB, IO_IS=DAC_SPI_MISO
PORT RFC_DAC_SPI_MISO = "", DIR = I, IO_IF=HW_Ports_RFC, IO_IS=DAC_SPI_MISO
PORT RFD_DAC_SPI_MISO = "", DIR = I, IO_IF=HW_Ports_RFD, IO_IS=DAC_SPI_MISO

PORT RFA_DAC_RESET = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=DAC_RESET
PORT RFB_DAC_RESET = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=DAC_RESET
PORT RFC_DAC_RESET = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=DAC_RESET
PORT RFD_DAC_RESET = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=DAC_RESET

PORT RFA_DAC_PLLLOCK = "", DIR = I, IO_IF=HW_Ports_RFA, IO_IS=DAC_PLLLOCK
PORT RFB_DAC_PLLLOCK = "", DIR = I, IO_IF=HW_Ports_RFB, IO_IS=DAC_PLLLOCK
PORT RFC_DAC_PLLLOCK = "", DIR = I, IO_IF=HW_Ports_RFC, IO_IS=DAC_PLLLOCK
PORT RFD_DAC_PLLLOCK = "", DIR = I, IO_IF=HW_Ports_RFD, IO_IS=DAC_PLLLOCK

#User ports - connect to application-specific ports in the FPGA
PORT usr_RFA_TxEn = "", DIR = I, IO_IF=User_Ports_RFA, IO_IS=TxEn
PORT usr_RFB_TxEn = "", DIR = I, IO_IF=User_Ports_RFB, IO_IS=TxEn
PORT usr_RFC_TxEn = "", DIR = I, IO_IF=User_Ports_RFC, IO_IS=TxEn
PORT usr_RFD_TxEn = "", DIR = I, IO_IF=User_Ports_RFD, IO_IS=TxEn

PORT usr_RFA_RxEn = "", DIR = I, IO_IF=User_Ports_RFA, IO_IS=RxEn
PORT usr_RFB_RxEn = "", DIR = I, IO_IF=User_Ports_RFB, IO_IS=RxEn
PORT usr_RFC_RxEn = "", DIR = I, IO_IF=User_Ports_RFC, IO_IS=RxEn
PORT usr_RFD_RxEn = "", DIR = I, IO_IF=User_Ports_RFD, IO_IS=RxEn

PORT usr_RFA_RxHP = "", DIR = I, IO_IF=User_Ports_RFA, IO_IS=RxHP
PORT usr_RFB_RxHP = "", DIR = I, IO_IF=User_Ports_RFB, IO_IS=RxHP
PORT usr_RFC_RxHP = "", DIR = I, IO_IF=User_Ports_RFC, IO_IS=RxHP
PORT usr_RFD_RxHP = "", DIR = I, IO_IF=User_Ports_RFD, IO_IS=RxHP

PORT usr_RFA_SHDN = "", DIR = I, IO_IF=User_Ports_RFA, IO_IS=SHDN
PORT usr_RFB_SHDN = "", DIR = I, IO_IF=User_Ports_RFB, IO_IS=SHDN
PORT usr_RFC_SHDN = "", DIR = I, IO_IF=User_Ports_RFC, IO_IS=SHDN
PORT usr_RFD_SHDN = "", DIR = I, IO_IF=User_Ports_RFD, IO_IS=SHDN

PORT usr_RFA_RxGainRF = "", DIR = I, VEC = [0:1], IO_IF=User_Ports_RFA, IO_IS=RxGainRF
PORT usr_RFB_RxGainRF = "", DIR = I, VEC = [0:1], IO_IF=User_Ports_RFB, IO_IS=RxGainRF
PORT usr_RFC_RxGainRF = "", DIR = I, VEC = [0:1], IO_IF=User_Ports_RFC, IO_IS=RxGainRF
PORT usr_RFD_RxGainRF = "", DIR = I, VEC = [0:1], IO_IF=User_Ports_RFD, IO_IS=RxGainRF

PORT usr_RFA_RxGainBB = "", DIR = I, VEC = [0:4], IO_IF=User_Ports_RFA, IO_IS=RxGainBB
PORT usr_RFB_RxGainBB = "", DIR = I, VEC = [0:4], IO_IF=User_Ports_RFB, IO_IS=RxGainBB
PORT usr_RFC_RxGainBB = "", DIR = I, VEC = [0:4], IO_IF=User_Ports_RFC, IO_IS=RxGainBB
PORT usr_RFD_RxGainBB = "", DIR = I, VEC = [0:4], IO_IF=User_Ports_RFD, IO_IS=RxGainBB

PORT usr_RFA_TxGain = "", DIR = I, VEC = [0:5], IO_IF=User_Ports_RFA, IO_IS=TxGain
PORT usr_RFB_TxGain = "", DIR = I, VEC = [0:5], IO_IF=User_Ports_RFB, IO_IS=TxGain
PORT usr_RFC_TxGain = "", DIR = I, VEC = [0:5], IO_IF=User_Ports_RFC, IO_IS=TxGain
PORT usr_RFD_TxGain = "", DIR = I, VEC = [0:5], IO_IF=User_Ports_RFD, IO_IS=TxGain

PORT usr_RFA_PHYStart = "", DIR = O, IO_IF=User_Ports_RFA, IO_IS=PHYStart
PORT usr_RFB_PHYStart = "", DIR = O, IO_IF=User_Ports_RFB, IO_IS=PHYStart
PORT usr_RFC_PHYStart = "", DIR = O, IO_IF=User_Ports_RFC, IO_IS=PHYStart
PORT usr_RFD_PHYStart = "", DIR = O, IO_IF=User_Ports_RFD, IO_IS=PHYStart

PORT usr_SPI_ctrlSrc = "", DIR = I, IO_IF=User_Ports_Misc, IO_IS=SPI_ctrlSrc
PORT usr_SPI_go = "", DIR = I, IO_IF=User_Ports_Misc, IO_IS=SPI_go
PORT usr_SPI_active = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=SPI_active
PORT usr_SPI_rfsel = "", DIR = I, VEC = [0:3], IO_IF=User_Ports_Misc, IO_IS=SPI_rfsel
PORT usr_SPI_regaddr = "", DIR = I, VEC = [0:3], IO_IF=User_Ports_Misc, IO_IS=SPI_regaddr
PORT usr_SPI_regdata = "", DIR = I, VEC = [0:13], IO_IF=User_Ports_Misc, IO_IS=SPI_regdata

PORT usr_any_PHYStart = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=any_PHYStart

#Status LED ports; these will typically connect directly to Radio Board LEDs via the radio_bridge
PORT usr_RFA_statLED_Tx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFA_statLED_Tx
PORT usr_RFB_statLED_Tx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFB_statLED_Tx
PORT usr_RFC_statLED_Tx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFC_statLED_Tx
PORT usr_RFD_statLED_Tx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFD_statLED_Tx

PORT usr_RFA_statLED_Rx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFA_statLED_Rx
PORT usr_RFB_statLED_Rx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFB_statLED_Rx
PORT usr_RFC_statLED_Rx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFC_statLED_Rx
PORT usr_RFD_statLED_Rx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFD_statLED_Rx

PORT usr_RFA_statLED_NoLock = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFA_statLED_NoLock
PORT usr_RFB_statLED_NoLock = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFB_statLED_NoLock
PORT usr_RFC_statLED_NoLock = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFC_statLED_NoLock
PORT usr_RFD_statLED_NoLock = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFD_statLED_NoLock

END