1 | ###################################################################
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2 | ##
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3 | ## Name : radio_controller
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4 | ## Desc : Microprocessor Peripheral Description
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5 | ## : Automatically generated by PsfUtility
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6 | ##
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7 | ###################################################################
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8 |
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9 | BEGIN radio_controller
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10 |
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11 | ## Peripheral Options
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12 | OPTION IPTYPE = PERIPHERAL
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13 | OPTION IMP_NETLIST = TRUE
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14 | OPTION HDL = MIXED
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15 | OPTION IP_GROUP = MICROBLAZE:PPC:USER
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16 | OPTION DESC = RADIO_CONTROLLER
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17 | OPTION ARCH_SUPPORT_MAP = (virtex4=DEVELOPMENT)
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18 |
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19 | IO_INTERFACE IO_IF = HW_Ports_RFA, IO_TYPE = W2_RADIOCONTROLLER_V0
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20 | IO_INTERFACE IO_IF = HW_Ports_RFB, IO_TYPE = W2_RADIOCONTROLLER_V0
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21 | IO_INTERFACE IO_IF = HW_Ports_RFC, IO_TYPE = W2_RADIOCONTROLLER_V0
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22 | IO_INTERFACE IO_IF = HW_Ports_RFD, IO_TYPE = W2_RADIOCONTROLLER_V0
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23 |
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24 | IO_INTERFACE IO_IF = USER_Ports_RFA, IO_TYPE = W2_RADIOCONTROLLER_V0
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25 | IO_INTERFACE IO_IF = USER_Ports_RFB, IO_TYPE = W2_RADIOCONTROLLER_V0
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26 | IO_INTERFACE IO_IF = USER_Ports_RFC, IO_TYPE = W2_RADIOCONTROLLER_V0
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27 | IO_INTERFACE IO_IF = USER_Ports_RFD, IO_TYPE = W2_RADIOCONTROLLER_V0
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28 |
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29 | IO_INTERFACE IO_IF = USER_Ports_Misc, IO_TYPE = W2_RADIOCONTROLLER_V0
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30 |
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31 | ## Bus Interfaces
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32 | BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
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33 |
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34 | ## Generics for VHDL or Parameters for Verilog
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35 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
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36 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
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37 | PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
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38 | PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
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39 | PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
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40 | PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
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41 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
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42 | PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
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43 | PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
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44 | PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
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45 | PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
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46 | PARAMETER C_INCLUDE_DPHASE_TIMER = 0, DT = INTEGER, RANGE = (0, 1)
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47 | PARAMETER C_FAMILY = virtex4, DT = STRING
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48 |
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49 | ## Ports
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50 | PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
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51 | PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
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52 | PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
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53 | PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
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54 | PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
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55 | PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
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56 | PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
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57 | PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
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58 | PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
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59 | PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
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60 | PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
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61 | PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
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62 | PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
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63 | PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
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64 | PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
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65 | PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
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66 | PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
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67 | PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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68 | PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
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69 | PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
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70 | PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
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71 | PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
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72 | PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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73 | PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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74 | PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
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75 | PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
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76 | PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
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77 | PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
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78 | PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
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79 | PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
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80 | PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
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81 | PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
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82 | PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
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83 | PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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84 | PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
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85 | PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
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86 | PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
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87 | PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
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88 | PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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89 | PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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90 | PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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91 | PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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92 |
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93 | PORT RFA_TxEn = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=TxEn
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94 | PORT RFB_TxEn = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=TxEn
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95 | PORT RFC_TxEn = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=TxEn
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96 | PORT RFD_TxEn = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=TxEn
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97 |
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98 | PORT RFA_RxEn = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=RxEn
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99 | PORT RFB_RxEn = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=RxEn
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100 | PORT RFC_RxEn = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=RxEn
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101 | PORT RFD_RxEn = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=RxEn
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102 |
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103 | PORT RFA_RxHP = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=RxHP
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104 | PORT RFB_RxHP = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=RxHP
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105 | PORT RFC_RxHP = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=RxHP
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106 | PORT RFD_RxHP = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=RxHP
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107 |
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108 | PORT RFA_SHDN = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=SHDN
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109 | PORT RFB_SHDN = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=SHDN
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110 | PORT RFC_SHDN = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=SHDN
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111 | PORT RFD_SHDN = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=SHDN
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112 |
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113 | PORT RFA_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=SPI_SCLK
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114 | PORT RFB_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=SPI_SCLK
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115 | PORT RFC_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=SPI_SCLK
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116 | PORT RFD_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=SPI_SCLK
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117 |
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118 | PORT RFA_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=SPI_MOSI
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119 | PORT RFB_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=SPI_MOSI
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120 | PORT RFC_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=SPI_MOSI
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121 | PORT RFD_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=SPI_MOSI
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122 |
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123 | PORT RFA_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=SPI_CSn
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124 | PORT RFB_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=SPI_CSn
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125 | PORT RFC_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=SPI_CSn
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126 | PORT RFD_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=SPI_CSn
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127 |
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128 | PORT RFA_B = "", DIR = O, VEC = [0:6], IO_IF=HW_Ports_RFA, IO_IS=B
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129 | PORT RFB_B = "", DIR = O, VEC = [0:6], IO_IF=HW_Ports_RFB, IO_IS=B
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130 | PORT RFC_B = "", DIR = O, VEC = [0:6], IO_IF=HW_Ports_RFC, IO_IS=B
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131 | PORT RFD_B = "", DIR = O, VEC = [0:6], IO_IF=HW_Ports_RFD, IO_IS=B
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132 |
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133 | PORT RFA_LD = "", DIR = I, IO_IF=HW_Ports_RFA, IO_IS=LD
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134 | PORT RFB_LD = "", DIR = I, IO_IF=HW_Ports_RFB, IO_IS=LD
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135 | PORT RFC_LD = "", DIR = I, IO_IF=HW_Ports_RFC, IO_IS=LD
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136 | PORT RFD_LD = "", DIR = I, IO_IF=HW_Ports_RFD, IO_IS=LD
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137 |
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138 | PORT RFA_PAEn_24 = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=PAEn_24
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139 | PORT RFB_PAEn_24 = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=PAEn_24
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140 | PORT RFC_PAEn_24 = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=PAEn_24
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141 | PORT RFD_PAEn_24 = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=PAEn_24
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142 |
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143 | PORT RFA_PAEn_5 = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=PAEn_5
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144 | PORT RFB_PAEn_5 = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=PAEn_5
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145 | PORT RFC_PAEn_5 = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=PAEn_5
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146 | PORT RFD_PAEn_5 = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=PAEn_5
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147 |
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148 | PORT RFA_AntSw = "", DIR = O, VEC = [0:1], IO_IF=HW_Ports_RFA, IO_IS=AntSw
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149 | PORT RFB_AntSw = "", DIR = O, VEC = [0:1], IO_IF=HW_Ports_RFB, IO_IS=AntSw
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150 | PORT RFC_AntSw = "", DIR = O, VEC = [0:1], IO_IF=HW_Ports_RFC, IO_IS=AntSw
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151 | PORT RFD_AntSw = "", DIR = O, VEC = [0:1], IO_IF=HW_Ports_RFD, IO_IS=AntSw
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152 |
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153 | PORT RFA_DIPSW = "", DIR = I, VEC = [0:3], IO_IF=HW_Ports_RFA, IO_IS=DIPSW
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154 | PORT RFB_DIPSW = "", DIR = I, VEC = [0:3], IO_IF=HW_Ports_RFB, IO_IS=DIPSW
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155 | PORT RFC_DIPSW = "", DIR = I, VEC = [0:3], IO_IF=HW_Ports_RFC, IO_IS=DIPSW
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156 | PORT RFD_DIPSW = "", DIR = I, VEC = [0:3], IO_IF=HW_Ports_RFD, IO_IS=DIPSW
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157 |
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158 | PORT RFA_RX_ADC_DCS = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=ADC_DCS
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159 | PORT RFB_RX_ADC_DCS = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=ADC_DCS
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160 | PORT RFC_RX_ADC_DCS = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=ADC_DCS
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161 | PORT RFD_RX_ADC_DCS = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=ADC_DCS
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162 |
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163 | PORT RFA_RX_ADC_DFS = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=ADC_DFS
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164 | PORT RFB_RX_ADC_DFS = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=ADC_DFS
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165 | PORT RFC_RX_ADC_DFS = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=ADC_DFS
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166 | PORT RFD_RX_ADC_DFS = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=ADC_DFS
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167 |
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168 | PORT RFA_RX_ADC_PWDN = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=ADC_PWDN
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169 | PORT RFB_RX_ADC_PWDN = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=ADC_PWDN
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170 | PORT RFC_RX_ADC_PWDN = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=ADC_PWDN
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171 | PORT RFD_RX_ADC_PWDN = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=ADC_PWDN
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172 |
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173 | PORT RFA_RSSI_ADC_CLAMP = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=RSSI_ADC_RSSI_ADC_CLAMP
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174 | PORT RFB_RSSI_ADC_CLAMP = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=RSSI_ADC_RSSI_ADC_CLAMP
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175 | PORT RFC_RSSI_ADC_CLAMP = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=RSSI_ADC_RSSI_ADC_CLAMP
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176 | PORT RFD_RSSI_ADC_CLAMP = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=RSSI_ADC_RSSI_ADC_CLAMP
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177 |
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178 | PORT RFA_RSSI_ADC_HIZ = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=RSSI_ADC_RSSI_ADC_HIZ
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179 | PORT RFB_RSSI_ADC_HIZ = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=RSSI_ADC_RSSI_ADC_HIZ
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180 | PORT RFC_RSSI_ADC_HIZ = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=RSSI_ADC_RSSI_ADC_HIZ
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181 | PORT RFD_RSSI_ADC_HIZ = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=RSSI_ADC_RSSI_ADC_HIZ
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182 |
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183 | PORT RFA_RSSI_ADC_SLEEP = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=RSSI_ADC_RSSI_ADC_SLEEP
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184 | PORT RFB_RSSI_ADC_SLEEP = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=RSSI_ADC_RSSI_ADC_SLEEP
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185 | PORT RFC_RSSI_ADC_SLEEP = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=RSSI_ADC_RSSI_ADC_SLEEP
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186 | PORT RFD_RSSI_ADC_SLEEP = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=RSSI_ADC_RSSI_ADC_SLEEP
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187 |
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188 | #DAC control ports (integrated into this radio controller, not a separate ad_controller core)
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189 | PORT RFA_DAC_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=DAC_SPI_CSn
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190 | PORT RFB_DAC_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=DAC_SPI_CSn
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191 | PORT RFC_DAC_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=DAC_SPI_CSn
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192 | PORT RFD_DAC_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=DAC_SPI_CSn
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193 |
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194 | PORT RFA_DAC_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=DAC_SPI_SCLK
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195 | PORT RFB_DAC_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=DAC_SPI_SCLK
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196 | PORT RFC_DAC_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=DAC_SPI_SCLK
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197 | PORT RFD_DAC_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=DAC_SPI_SCLK
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198 |
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199 | PORT RFA_DAC_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=DAC_SPI_MOSI
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200 | PORT RFB_DAC_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=DAC_SPI_MOSI
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201 | PORT RFC_DAC_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=DAC_SPI_MOSI
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202 | PORT RFD_DAC_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=DAC_SPI_MOSI
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203 |
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204 | PORT RFA_DAC_SPI_MISO = "", DIR = I, IO_IF=HW_Ports_RFA, IO_IS=DAC_SPI_MISO
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205 | PORT RFB_DAC_SPI_MISO = "", DIR = I, IO_IF=HW_Ports_RFB, IO_IS=DAC_SPI_MISO
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206 | PORT RFC_DAC_SPI_MISO = "", DIR = I, IO_IF=HW_Ports_RFC, IO_IS=DAC_SPI_MISO
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207 | PORT RFD_DAC_SPI_MISO = "", DIR = I, IO_IF=HW_Ports_RFD, IO_IS=DAC_SPI_MISO
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208 |
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209 | PORT RFA_DAC_RESET = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=DAC_RESET
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210 | PORT RFB_DAC_RESET = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=DAC_RESET
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211 | PORT RFC_DAC_RESET = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=DAC_RESET
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212 | PORT RFD_DAC_RESET = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=DAC_RESET
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213 |
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214 | PORT RFA_DAC_PLLLOCK = "", DIR = I, IO_IF=HW_Ports_RFA, IO_IS=DAC_PLLLOCK
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215 | PORT RFB_DAC_PLLLOCK = "", DIR = I, IO_IF=HW_Ports_RFB, IO_IS=DAC_PLLLOCK
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216 | PORT RFC_DAC_PLLLOCK = "", DIR = I, IO_IF=HW_Ports_RFC, IO_IS=DAC_PLLLOCK
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217 | PORT RFD_DAC_PLLLOCK = "", DIR = I, IO_IF=HW_Ports_RFD, IO_IS=DAC_PLLLOCK
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218 |
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219 | #User ports - connect to application-specific ports in the FPGA
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220 | PORT usr_RFA_TxEn = "", DIR = I, IO_IF=User_Ports_RFA, IO_IS=TxEn
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221 | PORT usr_RFB_TxEn = "", DIR = I, IO_IF=User_Ports_RFB, IO_IS=TxEn
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222 | PORT usr_RFC_TxEn = "", DIR = I, IO_IF=User_Ports_RFC, IO_IS=TxEn
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223 | PORT usr_RFD_TxEn = "", DIR = I, IO_IF=User_Ports_RFD, IO_IS=TxEn
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224 |
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225 | PORT usr_RFA_RxEn = "", DIR = I, IO_IF=User_Ports_RFA, IO_IS=RxEn
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226 | PORT usr_RFB_RxEn = "", DIR = I, IO_IF=User_Ports_RFB, IO_IS=RxEn
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227 | PORT usr_RFC_RxEn = "", DIR = I, IO_IF=User_Ports_RFC, IO_IS=RxEn
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228 | PORT usr_RFD_RxEn = "", DIR = I, IO_IF=User_Ports_RFD, IO_IS=RxEn
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229 |
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230 | PORT usr_RFA_RxHP = "", DIR = I, IO_IF=User_Ports_RFA, IO_IS=RxHP
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231 | PORT usr_RFB_RxHP = "", DIR = I, IO_IF=User_Ports_RFB, IO_IS=RxHP
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232 | PORT usr_RFC_RxHP = "", DIR = I, IO_IF=User_Ports_RFC, IO_IS=RxHP
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233 | PORT usr_RFD_RxHP = "", DIR = I, IO_IF=User_Ports_RFD, IO_IS=RxHP
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234 |
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235 | PORT usr_RFA_SHDN = "", DIR = I, IO_IF=User_Ports_RFA, IO_IS=SHDN
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236 | PORT usr_RFB_SHDN = "", DIR = I, IO_IF=User_Ports_RFB, IO_IS=SHDN
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237 | PORT usr_RFC_SHDN = "", DIR = I, IO_IF=User_Ports_RFC, IO_IS=SHDN
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238 | PORT usr_RFD_SHDN = "", DIR = I, IO_IF=User_Ports_RFD, IO_IS=SHDN
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239 |
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240 | PORT usr_RFA_RxGainRF = "", DIR = I, VEC = [0:1], IO_IF=User_Ports_RFA, IO_IS=RxGainRF
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241 | PORT usr_RFB_RxGainRF = "", DIR = I, VEC = [0:1], IO_IF=User_Ports_RFB, IO_IS=RxGainRF
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242 | PORT usr_RFC_RxGainRF = "", DIR = I, VEC = [0:1], IO_IF=User_Ports_RFC, IO_IS=RxGainRF
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243 | PORT usr_RFD_RxGainRF = "", DIR = I, VEC = [0:1], IO_IF=User_Ports_RFD, IO_IS=RxGainRF
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244 |
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245 | PORT usr_RFA_RxGainBB = "", DIR = I, VEC = [0:4], IO_IF=User_Ports_RFA, IO_IS=RxGainBB
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246 | PORT usr_RFB_RxGainBB = "", DIR = I, VEC = [0:4], IO_IF=User_Ports_RFB, IO_IS=RxGainBB
|
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247 | PORT usr_RFC_RxGainBB = "", DIR = I, VEC = [0:4], IO_IF=User_Ports_RFC, IO_IS=RxGainBB
|
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248 | PORT usr_RFD_RxGainBB = "", DIR = I, VEC = [0:4], IO_IF=User_Ports_RFD, IO_IS=RxGainBB
|
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249 |
|
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250 | PORT usr_RFA_TxGain = "", DIR = I, VEC = [0:5], IO_IF=User_Ports_RFA, IO_IS=TxGain
|
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251 | PORT usr_RFB_TxGain = "", DIR = I, VEC = [0:5], IO_IF=User_Ports_RFB, IO_IS=TxGain
|
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252 | PORT usr_RFC_TxGain = "", DIR = I, VEC = [0:5], IO_IF=User_Ports_RFC, IO_IS=TxGain
|
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253 | PORT usr_RFD_TxGain = "", DIR = I, VEC = [0:5], IO_IF=User_Ports_RFD, IO_IS=TxGain
|
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254 |
|
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255 | PORT usr_RFA_PHYStart = "", DIR = O, IO_IF=User_Ports_RFA, IO_IS=PHYStart
|
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256 | PORT usr_RFB_PHYStart = "", DIR = O, IO_IF=User_Ports_RFB, IO_IS=PHYStart
|
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257 | PORT usr_RFC_PHYStart = "", DIR = O, IO_IF=User_Ports_RFC, IO_IS=PHYStart
|
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258 | PORT usr_RFD_PHYStart = "", DIR = O, IO_IF=User_Ports_RFD, IO_IS=PHYStart
|
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259 |
|
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260 | PORT usr_SPI_ctrlSrc = "", DIR = I, IO_IF=User_Ports_Misc, IO_IS=SPI_ctrlSrc
|
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261 | PORT usr_SPI_go = "", DIR = I, IO_IF=User_Ports_Misc, IO_IS=SPI_go
|
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262 | PORT usr_SPI_active = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=SPI_active
|
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263 | PORT usr_SPI_rfsel = "", DIR = I, VEC = [0:3], IO_IF=User_Ports_Misc, IO_IS=SPI_rfsel
|
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264 | PORT usr_SPI_regaddr = "", DIR = I, VEC = [0:3], IO_IF=User_Ports_Misc, IO_IS=SPI_regaddr
|
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265 | PORT usr_SPI_regdata = "", DIR = I, VEC = [0:13], IO_IF=User_Ports_Misc, IO_IS=SPI_regdata
|
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266 |
|
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267 | PORT usr_any_PHYStart = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=any_PHYStart
|
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268 |
|
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269 | #Status LED ports; these will typically connect directly to Radio Board LEDs via the radio_bridge
|
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270 | PORT usr_RFA_statLED_Tx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFA_statLED_Tx
|
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271 | PORT usr_RFB_statLED_Tx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFB_statLED_Tx
|
---|
272 | PORT usr_RFC_statLED_Tx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFC_statLED_Tx
|
---|
273 | PORT usr_RFD_statLED_Tx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFD_statLED_Tx
|
---|
274 |
|
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275 | PORT usr_RFA_statLED_Rx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFA_statLED_Rx
|
---|
276 | PORT usr_RFB_statLED_Rx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFB_statLED_Rx
|
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277 | PORT usr_RFC_statLED_Rx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFC_statLED_Rx
|
---|
278 | PORT usr_RFD_statLED_Rx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFD_statLED_Rx
|
---|
279 |
|
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280 | PORT usr_RFA_statLED_NoLock = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFA_statLED_NoLock
|
---|
281 | PORT usr_RFB_statLED_NoLock = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFB_statLED_NoLock
|
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282 | PORT usr_RFC_statLED_NoLock = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFC_statLED_NoLock
|
---|
283 | PORT usr_RFD_statLED_NoLock = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFD_statLED_NoLock
|
---|
284 |
|
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285 | END
|
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