[2442] | 1 | BEGIN simple_spi
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[1927] | 2 |
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| 3 | ## Peripheral Options
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| 4 | OPTION IPTYPE = PERIPHERAL
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| 5 | OPTION IMP_NETLIST = TRUE
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| 6 | OPTION HDL = MIXED
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| 7 | OPTION IP_GROUP = MICROBLAZE:USER
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| 8 | OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
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| 9 | OPTION DESC = WARP v3 AD Controller (AXI)
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[2442] | 10 | OPTION LONG_DESC="Implements simple SPI master"
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[1927] | 11 |
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[2442] | 12 | IO_INTERFACE IO_IF = SPI_PINS, IO_TYPE = SPI_PINS
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[1927] | 13 |
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| 14 | ## Bus Interfaces
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| 15 | BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
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| 16 |
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| 17 | ## Generics for VHDL or Parameters for Verilog
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| 18 | PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
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| 19 | PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
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| 20 | PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
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| 21 | PARAMETER C_USE_WSTRB = 0, DT = INTEGER
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| 22 | PARAMETER C_DPHASE_TIMEOUT = 0, DT = INTEGER
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| 23 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
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| 24 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
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| 25 | PARAMETER C_FAMILY = virtex6, DT = STRING
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| 26 | PARAMETER C_NUM_REG = 1, DT = INTEGER
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| 27 | PARAMETER C_NUM_MEM = 1, DT = INTEGER
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| 28 | PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
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| 29 | PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
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| 30 | PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
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| 31 |
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| 32 | ## Ports
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| 33 | PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
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| 34 | PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
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| 35 | PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 36 | PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
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| 37 | PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 38 | PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 39 | PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
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| 40 | PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
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| 41 | PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 42 | PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
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| 43 | PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
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| 44 | PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
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| 45 | PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 46 | PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
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| 47 | PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
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| 48 | PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
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| 49 | PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
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| 50 | PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
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| 51 | PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI
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| 52 |
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[2442] | 53 | PORT spi_sclk = "", DIR = O, IO_IF=SPI_PINS, IO_IS=SPI_PINS_spi_sclk
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| 54 | PORT spi_cs_n = "", DIR = O, IO_IF=SPI_PINS, IO_IS=SPI_PINS_spi_cs_n
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| 55 | PORT spi_mosi = "", DIR = O, IO_IF=SPI_PINS, IO_IS=SPI_PINS_spi_mosi
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[2443] | 56 | PORT spi_miso = "", DIR = I, IO_IF=SPI_PINS, IO_IS=SPI_PINS_spi_miso
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[1927] | 57 |
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[2445] | 58 | PORT spi_enable_n = "", DIR = O, IO_IF=SPI_PINS, IO_IS=SPI_PINS_spi_enable_n
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| 59 | PORT cfg_req_n = "", DIR = O, IO_IF=SPI_PINS, IO_IS=SPI_PINS_cfg_req_n
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| 60 | PORT cfg_sel = "", DIR = O, VEC = [2:0], IO_IF=SPI_PINS, IO_IS=SPI_PINS_cfg_sel
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| 61 |
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[1927] | 62 | END
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