[6301] | 1 | BEGIN sw_intr_util
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| 2 |
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| 3 | ## Peripheral Options
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| 4 | OPTION IPTYPE = PERIPHERAL
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| 5 | OPTION IMP_NETLIST = TRUE
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| 6 | OPTION HDL = MIXED
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| 7 | OPTION IP_GROUP = MICROBLAZE:USER
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| 8 | OPTION DESC = SW_INTR_UTIL
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| 9 | OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
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| 10 |
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| 11 |
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| 12 | ## Bus Interfaces
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| 13 | BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
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| 14 |
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| 15 | ## Generics for VHDL or Parameters for Verilog
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| 16 | PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
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| 17 | PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
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| 18 | PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
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| 19 | PARAMETER C_USE_WSTRB = 0, DT = INTEGER
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| 20 | PARAMETER C_DPHASE_TIMEOUT = 8, DT = INTEGER
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| 21 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
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| 22 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
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| 23 | PARAMETER C_FAMILY = virtex6, DT = STRING
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| 24 | PARAMETER C_NUM_REG = 1, DT = INTEGER
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| 25 | PARAMETER C_NUM_MEM = 1, DT = INTEGER
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| 26 | PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
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| 27 | PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
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| 28 | PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
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| 29 |
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| 30 | ## Ports
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| 31 | PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
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| 32 | PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
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| 33 | PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 34 | PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
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| 35 | PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 36 | PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 37 | PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
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| 38 | PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
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| 39 | PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 40 | PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
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| 41 | PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
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| 42 | PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
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| 43 | PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 44 | PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
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| 45 | PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
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| 46 | PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
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| 47 | PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
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| 48 | PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
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| 49 | PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI
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| 50 |
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[6302] | 51 | PORT intrA_out = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH, INTERRUPT_PRIORITY = HIGH
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| 52 | PORT intrB_out = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH, INTERRUPT_PRIORITY = HIGH
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| 53 |
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[6301] | 54 | END
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