source: PlatformSupport/CustomPeripherals/pcores/sw_intr_util_v1_00_a/src/sw_intr_util.h

/*****************************************************************
* File: sw_intr_util.h
* Copyright (c) 2018 Mango Communications, all rights reseved
*****************************************************************/

#ifndef SW_INTR_UTIL_H
#define SW_INTR_UTIL_H

/***************************** Include Files *******************************/

#include "xstatus.h"
#include "xil_io.h"

#define SW_INTR_UTIL_USER_SLV_SPACE_OFFSET (0x00000000)
#define SW_INTR_UTIL_SLV_REG0_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000000)
#define SW_INTR_UTIL_SLV_REG1_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000004)
#define SW_INTR_UTIL_SLV_REG2_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000008)
#define SW_INTR_UTIL_SLV_REG3_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x0000000C)
#define SW_INTR_UTIL_SLV_REG4_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000010)
#define SW_INTR_UTIL_SLV_REG5_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000014)
#define SW_INTR_UTIL_SLV_REG6_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000018)
#define SW_INTR_UTIL_SLV_REG7_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x0000001C)
#define SW_INTR_UTIL_SLV_REG8_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000020)
#define SW_INTR_UTIL_SLV_REG9_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000024)
#define SW_INTR_UTIL_SLV_REG10_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000028)
#define SW_INTR_UTIL_SLV_REG11_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x0000002C)
#define SW_INTR_UTIL_SLV_REG12_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000030)
#define SW_INTR_UTIL_SLV_REG13_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000034)
#define SW_INTR_UTIL_SLV_REG14_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000038)
#define SW_INTR_UTIL_SLV_REG15_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x0000003C)

/* Address map:
    HDL is coded [MSB:LSB] = [31:0], per Xilinx's convention for AXI peripherals
    regX[31] maps to 0x80000000 in C driver
    regX[ 0] maps to 0x00000001 in C driver

0: RO/RW: Control/status register
    [    0] = Enable (active high) for intrA output
    [    1] = Enable (active high) for intrB output
    [   28] = (RO) current intrA_out value
    [   29] = (RO) current intrB_out value
    
1: RW: Software state register 0
2: RW: Software state register 1

3: RW: Bitmask for sw state reg 0 asserting intrA
4: RW: Bitmask for sw state reg 1 asserting intrA
5: RW: Bitmask for sw state reg 0 asserting intrB
6: RW: Bitmask for sw state reg 1 asserting intrB

Two interrupt outputs - intrA and intrB. These should be connected
to an interrupt controller in the hardware design.

Either software state register can assert either interrupt output.

intrA is asserted when en_intrA & (((sw_state0 & sw_mask0_A) || (sw_state1 & sw_mask1_A)) != 0)
intrB is asserted when en_intrB & (((sw_state0 & sw_mask0_B) || (sw_state1 & sw_mask1_B)) != 0)

*/  

#define SW_INTR_CTRL_REG_EN_A   0x00000001
#define SW_INTR_CTRL_REG_EN_B   0x00000002

#define SW_INTR_CTRL_REG_INTR_A 0x10000000
#define SW_INTR_CTRL_REG_INTR_B 0x20000000

#define sw_intr_set_enA(ba, e) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG0_OFFSET, (Xil_In32((ba) + SW_INTR_UTIL_SLV_REG0_OFFSET) & ~SW_INTR_CTRL_REG_EN_A) | ((e) ? SW_INTR_CTRL_REG_EN_A : 0))
#define sw_intr_set_enB(ba, e) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG0_OFFSET, (Xil_In32((ba) + SW_INTR_UTIL_SLV_REG0_OFFSET) & ~SW_INTR_CTRL_REG_EN_B) | ((e) ? SW_INTR_CTRL_REG_EN_B : 0))

#define sw_intr_get_enA(ba) ((Xil_In32((ba) + SW_INTR_UTIL_SLV_REG0_OFFSET) & SW_INTR_CTRL_REG_EN_A) ? 1 : 0)
#define sw_intr_get_enB(ba) ((Xil_In32((ba) + SW_INTR_UTIL_SLV_REG0_OFFSET) & SW_INTR_CTRL_REG_EN_B) ? 1 : 0)

#define sw_intr_set_state0(ba, s) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG1_OFFSET, (s))
#define sw_intr_set_state1(ba, s) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG2_OFFSET, (s))

#define sw_intr_get_state0(ba) Xil_In32((ba) + SW_INTR_UTIL_SLV_REG1_OFFSET)
#define sw_intr_get_state1(ba) Xil_In32((ba) + SW_INTR_UTIL_SLV_REG2_OFFSET)

#define sw_intr_set_mask_A0(ba, m) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG3_OFFSET, (m))
#define sw_intr_set_mask_A1(ba, m) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG4_OFFSET, (m))
#define sw_intr_set_mask_B0(ba, m) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG5_OFFSET, (m))
#define sw_intr_set_mask_B1(ba, m) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG6_OFFSET, (m))

#define sw_intr_get_mask_A0(ba) Xil_In32((ba) + SW_INTR_UTIL_SLV_REG3_OFFSET)
#define sw_intr_get_mask_A1(ba) Xil_In32((ba) + SW_INTR_UTIL_SLV_REG4_OFFSET)
#define sw_intr_get_mask_B0(ba) Xil_In32((ba) + SW_INTR_UTIL_SLV_REG5_OFFSET)
#define sw_intr_get_mask_B1(ba) Xil_In32((ba) + SW_INTR_UTIL_SLV_REG6_OFFSET)

void sw_intr_init(u32 baseaddr);


#endif /** SW_INTR_UTIL_H */