[6302] | 1 | /***************************************************************** |
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| 2 | * File: sw_intr_util.h |
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| 3 | * Copyright (c) 2018 Mango Communications, all rights reseved |
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| 4 | *****************************************************************/ |
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[6301] | 5 | |
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| 6 | #ifndef SW_INTR_UTIL_H |
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| 7 | #define SW_INTR_UTIL_H |
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| 8 | |
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| 9 | /***************************** Include Files *******************************/ |
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| 10 | |
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| 11 | #include "xstatus.h" |
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| 12 | #include "xil_io.h" |
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| 13 | |
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| 14 | #define SW_INTR_UTIL_USER_SLV_SPACE_OFFSET (0x00000000) |
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| 15 | #define SW_INTR_UTIL_SLV_REG0_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000000) |
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| 16 | #define SW_INTR_UTIL_SLV_REG1_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000004) |
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| 17 | #define SW_INTR_UTIL_SLV_REG2_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000008) |
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| 18 | #define SW_INTR_UTIL_SLV_REG3_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x0000000C) |
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| 19 | #define SW_INTR_UTIL_SLV_REG4_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000010) |
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| 20 | #define SW_INTR_UTIL_SLV_REG5_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000014) |
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| 21 | #define SW_INTR_UTIL_SLV_REG6_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000018) |
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| 22 | #define SW_INTR_UTIL_SLV_REG7_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x0000001C) |
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| 23 | #define SW_INTR_UTIL_SLV_REG8_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000020) |
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| 24 | #define SW_INTR_UTIL_SLV_REG9_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000024) |
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| 25 | #define SW_INTR_UTIL_SLV_REG10_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000028) |
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| 26 | #define SW_INTR_UTIL_SLV_REG11_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x0000002C) |
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| 27 | #define SW_INTR_UTIL_SLV_REG12_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000030) |
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| 28 | #define SW_INTR_UTIL_SLV_REG13_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000034) |
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| 29 | #define SW_INTR_UTIL_SLV_REG14_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x00000038) |
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| 30 | #define SW_INTR_UTIL_SLV_REG15_OFFSET (SW_INTR_UTIL_USER_SLV_SPACE_OFFSET + 0x0000003C) |
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| 31 | |
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[6305] | 32 | /* Address map: |
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| 33 | HDL is coded [MSB:LSB] = [31:0], per Xilinx's convention for AXI peripherals |
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| 34 | regX[31] maps to 0x80000000 in C driver |
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| 35 | regX[ 0] maps to 0x00000001 in C driver |
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| 36 | |
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| 37 | 0: RO/RW: Control/status register |
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| 38 | [ 0] = Enable (active high) for intrA output |
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| 39 | [ 1] = Enable (active high) for intrB output |
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| 40 | [ 28] = (RO) current intrA_out value |
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| 41 | [ 29] = (RO) current intrB_out value |
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| 42 | |
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| 43 | 1: RW: Software state register 0 |
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| 44 | 2: RW: Software state register 1 |
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| 45 | |
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| 46 | 3: RW: Bitmask for sw state reg 0 asserting intrA |
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| 47 | 4: RW: Bitmask for sw state reg 1 asserting intrA |
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| 48 | 5: RW: Bitmask for sw state reg 0 asserting intrB |
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| 49 | 6: RW: Bitmask for sw state reg 1 asserting intrB |
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| 50 | |
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| 51 | Two interrupt outputs - intrA and intrB. These should be connected |
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| 52 | to an interrupt controller in the hardware design. |
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| 53 | |
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| 54 | Either software state register can assert either interrupt output. |
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| 55 | |
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| 56 | intrA is asserted when en_intrA & (((sw_state0 & sw_mask0_A) || (sw_state1 & sw_mask1_A)) != 0) |
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| 57 | intrB is asserted when en_intrB & (((sw_state0 & sw_mask0_B) || (sw_state1 & sw_mask1_B)) != 0) |
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| 58 | |
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| 59 | */ |
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| 60 | |
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| 61 | #define SW_INTR_CTRL_REG_EN_A 0x00000001 |
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| 62 | #define SW_INTR_CTRL_REG_EN_B 0x00000002 |
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| 63 | |
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| 64 | #define SW_INTR_CTRL_REG_INTR_A 0x10000000 |
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| 65 | #define SW_INTR_CTRL_REG_INTR_B 0x20000000 |
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| 66 | |
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| 67 | #define sw_intr_set_enA(ba, e) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG0_OFFSET, (Xil_In32((ba) + SW_INTR_UTIL_SLV_REG0_OFFSET) & ~SW_INTR_CTRL_REG_EN_A) | ((e) ? SW_INTR_CTRL_REG_EN_A : 0)) |
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| 68 | #define sw_intr_set_enB(ba, e) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG0_OFFSET, (Xil_In32((ba) + SW_INTR_UTIL_SLV_REG0_OFFSET) & ~SW_INTR_CTRL_REG_EN_B) | ((e) ? SW_INTR_CTRL_REG_EN_B : 0)) |
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| 69 | |
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[6318] | 70 | #define sw_intr_get_enA(ba) ((Xil_In32((ba) + SW_INTR_UTIL_SLV_REG0_OFFSET) & SW_INTR_CTRL_REG_EN_A) ? 1 : 0) |
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| 71 | #define sw_intr_get_enB(ba) ((Xil_In32((ba) + SW_INTR_UTIL_SLV_REG0_OFFSET) & SW_INTR_CTRL_REG_EN_B) ? 1 : 0) |
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| 72 | |
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[6305] | 73 | #define sw_intr_set_state0(ba, s) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG1_OFFSET, (s)) |
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| 74 | #define sw_intr_set_state1(ba, s) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG2_OFFSET, (s)) |
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| 75 | |
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[6306] | 76 | #define sw_intr_get_state0(ba) Xil_In32((ba) + SW_INTR_UTIL_SLV_REG1_OFFSET) |
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| 77 | #define sw_intr_get_state1(ba) Xil_In32((ba) + SW_INTR_UTIL_SLV_REG2_OFFSET) |
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| 78 | |
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[6305] | 79 | #define sw_intr_set_mask_A0(ba, m) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG3_OFFSET, (m)) |
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| 80 | #define sw_intr_set_mask_A1(ba, m) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG4_OFFSET, (m)) |
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| 81 | #define sw_intr_set_mask_B0(ba, m) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG5_OFFSET, (m)) |
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| 82 | #define sw_intr_set_mask_B1(ba, m) Xil_Out32((ba) + SW_INTR_UTIL_SLV_REG6_OFFSET, (m)) |
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| 83 | |
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[6318] | 84 | #define sw_intr_get_mask_A0(ba) Xil_In32((ba) + SW_INTR_UTIL_SLV_REG3_OFFSET) |
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| 85 | #define sw_intr_get_mask_A1(ba) Xil_In32((ba) + SW_INTR_UTIL_SLV_REG4_OFFSET) |
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| 86 | #define sw_intr_get_mask_B0(ba) Xil_In32((ba) + SW_INTR_UTIL_SLV_REG5_OFFSET) |
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| 87 | #define sw_intr_get_mask_B1(ba) Xil_In32((ba) + SW_INTR_UTIL_SLV_REG6_OFFSET) |
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| 88 | |
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[6305] | 89 | void sw_intr_init(u32 baseaddr); |
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| 90 | |
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| 91 | |
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[6301] | 92 | #endif /** SW_INTR_UTIL_H */ |
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