1 | module w3_ad_bridge |
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2 | ( |
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3 | //Ref clk for IDELAYCTRL |
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4 | input clk200, |
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5 | |
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6 | //Input sampling clocks - User design must provide these clock signals |
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7 | |
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8 | // sys_samp_clk_Tx requirements: |
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9 | // -Synchronous to and valid for capturing user_RFx_TXD ports |
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10 | // -Frequency must match AD9963 input data rate configuration (DAC clock / interpolation rate) |
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11 | input sys_samp_clk_Tx, |
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12 | |
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13 | // sys_samp_clk_Tx_90 must be 90 degree phase shift of sys_samp_clk_Tx (used to generate TXCLK output) |
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14 | input sys_samp_clk_Tx_90, |
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15 | |
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16 | // sys_samp_clk_Rx requirements: |
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17 | // -Synchronous to AD9963 ADC clock |
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18 | // -Frequency must match AD9963 output data rate configuration (ADC clock / decimation rate) |
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19 | // user_RFx_RXD outputs are synchronous to sys_samp_clk_Rx |
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20 | input sys_samp_clk_Rx, |
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21 | |
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22 | //RF Path A User Ports |
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23 | output [0:11] user_RFA_RXD_I, |
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24 | output [0:11] user_RFA_RXD_Q, |
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25 | |
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26 | input [0:11] user_RFA_TXD_I, |
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27 | input [0:11] user_RFA_TXD_Q, |
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28 | |
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29 | input user_RFA_TXIQ, |
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30 | |
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31 | //RF Path B User Ports |
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32 | output [0:11] user_RFB_RXD_I, |
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33 | output [0:11] user_RFB_RXD_Q, |
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34 | |
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35 | input [0:11] user_RFB_TXD_I, |
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36 | input [0:11] user_RFB_TXD_Q, |
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37 | |
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38 | input user_RFB_TXIQ, |
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39 | |
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40 | //RF Path A AD ports |
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41 | output [0:11] ad_RFA_TXD, |
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42 | output ad_RFA_TXIQ, |
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43 | output ad_RFA_TXCLK, |
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44 | |
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45 | input [0:11] ad_RFA_TRXD, |
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46 | input ad_RFA_TRXIQ, |
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47 | input ad_RFA_TRXCLK, |
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48 | |
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49 | //RF Path B AD ports |
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50 | output [0:11] ad_RFB_TXD, |
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51 | output ad_RFB_TXIQ, |
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52 | output ad_RFB_TXCLK, |
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53 | |
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54 | input [0:11] ad_RFB_TRXD, |
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55 | input ad_RFB_TRXIQ, |
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56 | input ad_RFB_TRXCLK |
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57 | ); |
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58 | |
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59 | parameter C_FAMILY = "virtex6"; |
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60 | parameter INCLUDE_IDELAYCTRL = 1; |
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61 | |
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62 | |
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63 | assign ad_RFA_TXIQ = user_RFA_TXIQ; |
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64 | assign ad_RFB_TXIQ = user_RFB_TXIQ; |
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65 | |
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66 | generate |
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67 | if(INCLUDE_IDELAYCTRL==1) begin |
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68 | IDELAYCTRL IDELAYCTRL_inst ( |
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69 | .RDY(), // 1-bit Ready output |
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70 | .REFCLK(clk200), // 1-bit Reference clock input |
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71 | .RST(1'b0) // 1-bit Reset input |
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72 | ); |
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73 | end |
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74 | endgenerate |
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75 | |
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76 | //Use DDR primitives for cleanest output clock |
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77 | ODDR #( |
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78 | .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" |
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79 | .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 |
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80 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
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81 | ) OBUFDDR_RFA_TXCLK ( |
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82 | .Q(ad_RFA_TXCLK), // 1-bit DDR output |
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83 | .C(sys_samp_clk_Tx_90), // 1-bit clock input |
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84 | .CE(1'b1), // 1-bit clock enable input |
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85 | .D1(1'b1), // 1-bit data input (positive edge) |
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86 | .D2(1'b0), // 1-bit data input (negative edge) |
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87 | .R(1'b0), // 1-bit reset |
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88 | .S(1'b0) // 1-bit set |
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89 | ); |
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90 | |
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91 | ODDR #( |
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92 | .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" |
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93 | .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 |
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94 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
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95 | ) OBUFDDR_RFB_TXCLK ( |
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96 | .Q(ad_RFB_TXCLK), // 1-bit DDR output |
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97 | .C(sys_samp_clk_Tx_90), // 1-bit clock input |
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98 | .CE(1'b1), // 1-bit clock enable input |
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99 | .D1(1'b1), // 1-bit data input (positive edge) |
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100 | .D2(1'b0), // 1-bit data input (negative edge) |
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101 | .R(1'b0), // 1-bit reset |
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102 | .S(1'b0) // 1-bit set |
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103 | ); |
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104 | |
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105 | |
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106 | wire ad_RFA_TRXCLK_buf, ad_RFB_TRXCLK_buf; |
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107 | wire ad_RFA_TRXCLK_dly, ad_RFB_TRXCLK_dly; |
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108 | |
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109 | //Delay AD9963-generated TRXCLK, then drive BUFIO for latching TRXD DDR inputs |
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110 | IODELAYE1 #( |
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111 | .CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion ("TRUE"/"FALSE") |
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112 | .DELAY_SRC("I"), // Delay input ("I", "CLKIN", "DATAIN", "IO", "O") |
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113 | .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE") |
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114 | .IDELAY_TYPE("FIXED"), // "FIXED", "VARIABLE", or "VAR_LOADABLE" |
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115 | .IDELAY_VALUE(31), // Output delay tap setting (0-32) |
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116 | .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz |
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117 | .SIGNAL_PATTERN("CLOCK") // "DATA" or "CLOCK" input signal |
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118 | ) IDELAY_RFA_TRXCLK ( |
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119 | .IDATAIN(ad_RFA_TRXCLK), |
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120 | .DATAOUT(ad_RFA_TRXCLK_dly), |
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121 | .T(1'b0) // 1-bit input - 3-state input control. Tie high for input-only or internal delay or |
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122 | ); |
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123 | |
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124 | IODELAYE1 #( |
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125 | .CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion ("TRUE"/"FALSE") |
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126 | .DELAY_SRC("I"), // Delay input ("I", "CLKIN", "DATAIN", "IO", "O") |
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127 | .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE") |
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128 | .IDELAY_TYPE("FIXED"), // "FIXED", "VARIABLE", or "VAR_LOADABLE" |
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129 | .IDELAY_VALUE(31), // Output delay tap setting (0-32) |
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130 | .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz |
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131 | .SIGNAL_PATTERN("CLOCK") // "DATA" or "CLOCK" input signal |
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132 | ) IDELAY_RFB_TRXCLK ( |
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133 | .IDATAIN(ad_RFB_TRXCLK), |
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134 | .DATAOUT(ad_RFB_TRXCLK_dly), |
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135 | .T(1'b0) // 1-bit input - 3-state input control. Tie high for input-only or internal delay or |
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136 | ); |
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137 | |
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138 | BUFIO BUFIO_RFA_TRXCLK ( |
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139 | .O(ad_RFA_TRXCLK_buf), // Clock buffer output |
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140 | .I(ad_RFA_TRXCLK_dly) // Clock buffer input |
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141 | ); |
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142 | |
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143 | BUFIO BUFIO_RFB_TRXCLK ( |
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144 | .O(ad_RFB_TRXCLK_buf), // Clock buffer output |
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145 | .I(ad_RFB_TRXCLK_dly) // Clock buffer input |
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146 | ); |
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147 | |
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148 | wire [0:11] user_RFA_RXD_I_src; |
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149 | wire [0:11] user_RFA_RXD_Q_src; |
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150 | wire [0:11] user_RFB_RXD_I_src; |
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151 | wire [0:11] user_RFB_RXD_Q_src; |
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152 | |
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153 | //Instantiate all the DDR registers for TXD and TRXD I/O |
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154 | // Only selects bits [0:11] (12MSB) of 14-bit Tx I/Q samples provided by user logic |
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155 | genvar ii; |
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156 | generate |
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157 | for(ii=0; ii<12; ii=ii+1) begin: DDR_REGS_RFA_RFB |
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158 | ODDR #( |
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159 | .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" |
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160 | .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 |
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161 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
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162 | ) ODDR_RFA_TXD ( |
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163 | .Q(ad_RFA_TXD[ii]), // 1-bit DDR output |
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164 | .C(sys_samp_clk_Tx), // 1-bit clock input |
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165 | .CE(1'b1), // 1-bit clock enable input |
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166 | .D1(user_RFA_TXD_I[ii]), // 1-bit data input (positive edge) |
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167 | .D2(user_RFA_TXD_Q[ii]), // 1-bit data input (negative edge) |
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168 | .R(1'b0), // 1-bit reset |
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169 | .S(1'b0) // 1-bit set |
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170 | ); |
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171 | ODDR #( |
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172 | .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" |
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173 | .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 |
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174 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
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175 | ) ODDR_RFB_TXD ( |
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176 | .Q(ad_RFB_TXD[ii]), // 1-bit DDR output |
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177 | .C(sys_samp_clk_Tx), // 1-bit clock input |
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178 | .CE(1'b1), // 1-bit clock enable input |
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179 | .D1(user_RFB_TXD_I[ii]), // 1-bit data input (positive edge) |
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180 | .D2(user_RFB_TXD_Q[ii]), // 1-bit data input (negative edge) |
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181 | .R(1'b0), // 1-bit reset |
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182 | .S(1'b0) // 1-bit set |
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183 | ); |
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184 | |
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185 | |
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186 | IDDR #( |
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187 | .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" |
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188 | .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1 |
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189 | .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1 |
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190 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
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191 | ) IDDR_RFA_TRXD ( |
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192 | .Q1(user_RFA_RXD_I_src[ii]), // 1-bit output for positive edge of clock |
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193 | .Q2(user_RFA_RXD_Q_src[ii]), // 1-bit output for negative edge of clock |
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194 | .C(ad_RFA_TRXCLK_buf), // 1-bit clock input |
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195 | .CE(1'b1), // 1-bit clock enable input |
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196 | .D(ad_RFA_TRXD[ii]), // 1-bit DDR data input |
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197 | .R(1'b0), // 1-bit reset |
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198 | .S(1'b0) // 1-bit set |
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199 | ); |
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200 | IDDR #( |
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201 | .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" |
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202 | .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1 |
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203 | .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1 |
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204 | .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" |
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205 | ) IDDR_RFB_TRXD ( |
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206 | .Q1(user_RFB_RXD_I_src[ii]), // 1-bit output for positive edge of clock |
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207 | .Q2(user_RFB_RXD_Q_src[ii]), // 1-bit output for negative edge of clock |
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208 | .C(ad_RFB_TRXCLK_buf), // 1-bit clock input |
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209 | .CE(1'b1), // 1-bit clock enable input |
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210 | .D(ad_RFB_TRXD[ii]), // 1-bit DDR data input |
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211 | .R(1'b0), // 1-bit reset |
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212 | .S(1'b0) // 1-bit set |
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213 | ); |
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214 | |
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215 | //D flip flops to connect source-syncronous inputs to samp_clk domain (TRXCLK and samp_clk have same rate, arbitrary phases) |
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216 | FDSE #(.INIT(1'b0)) DFF2_RFA_I (.D(user_RFA_RXD_I_src[ii]), .Q(user_RFA_RXD_I[ii]), .C(sys_samp_clk_Rx), .S(1'b0), .CE(1'b1)); |
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217 | FDSE #(.INIT(1'b0)) DFF2_RFA_Q (.D(user_RFA_RXD_Q_src[ii]), .Q(user_RFA_RXD_Q[ii]), .C(sys_samp_clk_Rx), .S(1'b0), .CE(1'b1)); |
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218 | FDSE #(.INIT(1'b0)) DFF2_RFB_I (.D(user_RFB_RXD_I_src[ii]), .Q(user_RFB_RXD_I[ii]), .C(sys_samp_clk_Rx), .S(1'b0), .CE(1'b1)); |
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219 | FDSE #(.INIT(1'b0)) DFF2_RFB_Q (.D(user_RFB_RXD_Q_src[ii]), .Q(user_RFB_RXD_Q[ii]), .C(sys_samp_clk_Rx), .S(1'b0), .CE(1'b1)); |
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220 | end |
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221 | endgenerate |
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222 | |
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223 | endmodule |
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