1 | ------------------------------------------------------------------------------ |
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2 | -- w3_ad_controller_axi.vhd - entity/architecture pair |
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3 | ------------------------------------------------------------------------------ |
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4 | -- IMPORTANT: |
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5 | -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. |
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6 | -- |
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7 | -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. |
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8 | -- |
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9 | -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW |
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10 | -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION |
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11 | -- OF THE USER_LOGIC ENTITY. |
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12 | ------------------------------------------------------------------------------ |
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13 | -- |
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14 | -- *************************************************************************** |
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15 | -- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** |
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16 | -- ** ** |
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17 | -- ** Xilinx, Inc. ** |
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18 | -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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19 | -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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20 | -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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21 | -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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22 | -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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23 | -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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24 | -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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25 | -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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26 | -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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27 | -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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28 | -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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29 | -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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30 | -- ** FOR A PARTICULAR PURPOSE. ** |
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31 | -- ** ** |
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32 | -- *************************************************************************** |
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33 | -- |
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34 | ------------------------------------------------------------------------------ |
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35 | -- Filename: w3_ad_controller_axi.vhd |
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36 | -- Version: 3.01.a |
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37 | -- Description: Top level design, instantiates library components and user logic. |
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38 | -- Date: Tue Feb 26 12:57:13 2013 (by Create and Import Peripheral Wizard) |
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39 | -- VHDL Standard: VHDL'93 |
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40 | ------------------------------------------------------------------------------ |
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41 | -- Naming Conventions: |
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42 | -- active low signals: "*_n" |
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43 | -- clock signals: "clk", "clk_div#", "clk_#x" |
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44 | -- reset signals: "rst", "rst_n" |
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45 | -- generics: "C_*" |
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46 | -- user defined types: "*_TYPE" |
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47 | -- state machine next state: "*_ns" |
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48 | -- state machine current state: "*_cs" |
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49 | -- combinatorial signals: "*_com" |
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50 | -- pipelined or register delay signals: "*_d#" |
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51 | -- counter signals: "*cnt*" |
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52 | -- clock enable signals: "*_ce" |
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53 | -- internal version of output port: "*_i" |
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54 | -- device pins: "*_pin" |
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55 | -- ports: "- Names begin with Uppercase" |
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56 | -- processes: "*_PROCESS" |
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57 | -- component instantiations: "<ENTITY_>I_<#|FUNC>" |
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58 | ------------------------------------------------------------------------------ |
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59 | |
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60 | library ieee; |
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61 | use ieee.std_logic_1164.all; |
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62 | use ieee.std_logic_arith.all; |
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63 | use ieee.std_logic_unsigned.all; |
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64 | |
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65 | library proc_common_v3_00_a; |
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66 | use proc_common_v3_00_a.proc_common_pkg.all; |
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67 | use proc_common_v3_00_a.ipif_pkg.all; |
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68 | |
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69 | library axi_lite_ipif_v1_01_a; |
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70 | use axi_lite_ipif_v1_01_a.axi_lite_ipif; |
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71 | |
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72 | ------------------------------------------------------------------------------ |
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73 | -- Entity section |
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74 | ------------------------------------------------------------------------------ |
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75 | -- Definition of Generics: |
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76 | -- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width |
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77 | -- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width |
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78 | -- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size |
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79 | -- C_USE_WSTRB -- AXI4LITE slave: Write Strobe |
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80 | -- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout |
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81 | -- C_BASEADDR -- AXI4LITE slave: base address |
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82 | -- C_HIGHADDR -- AXI4LITE slave: high address |
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83 | -- C_FAMILY -- FPGA Family |
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84 | -- C_NUM_REG -- Number of software accessible registers |
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85 | -- C_NUM_MEM -- Number of address-ranges |
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86 | -- C_SLV_AWIDTH -- Slave interface address bus width |
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87 | -- C_SLV_DWIDTH -- Slave interface data bus width |
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88 | -- |
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89 | -- Definition of Ports: |
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90 | -- S_AXI_ACLK -- AXI4LITE slave: Clock |
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91 | -- S_AXI_ARESETN -- AXI4LITE slave: Reset |
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92 | -- S_AXI_AWADDR -- AXI4LITE slave: Write address |
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93 | -- S_AXI_AWVALID -- AXI4LITE slave: Write address valid |
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94 | -- S_AXI_WDATA -- AXI4LITE slave: Write data |
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95 | -- S_AXI_WSTRB -- AXI4LITE slave: Write strobe |
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96 | -- S_AXI_WVALID -- AXI4LITE slave: Write data valid |
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97 | -- S_AXI_BREADY -- AXI4LITE slave: Response ready |
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98 | -- S_AXI_ARADDR -- AXI4LITE slave: Read address |
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99 | -- S_AXI_ARVALID -- AXI4LITE slave: Read address valid |
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100 | -- S_AXI_RREADY -- AXI4LITE slave: Read data ready |
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101 | -- S_AXI_ARREADY -- AXI4LITE slave: read addres ready |
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102 | -- S_AXI_RDATA -- AXI4LITE slave: Read data |
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103 | -- S_AXI_RRESP -- AXI4LITE slave: Read data response |
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104 | -- S_AXI_RVALID -- AXI4LITE slave: Read data valid |
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105 | -- S_AXI_WREADY -- AXI4LITE slave: Write data ready |
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106 | -- S_AXI_BRESP -- AXI4LITE slave: Response |
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107 | -- S_AXI_BVALID -- AXI4LITE slave: Resonse valid |
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108 | -- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready |
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109 | ------------------------------------------------------------------------------ |
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110 | |
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111 | entity w3_ad_controller_axi is |
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112 | generic |
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113 | ( |
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114 | -- ADD USER GENERICS BELOW THIS LINE --------------- |
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115 | INCLUDE_RFC_RFD_IO : integer := 0; |
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116 | -- ADD USER GENERICS ABOVE THIS LINE --------------- |
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117 | |
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118 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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119 | -- Bus protocol parameters, do not add to or delete |
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120 | C_S_AXI_DATA_WIDTH : integer := 32; |
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121 | C_S_AXI_ADDR_WIDTH : integer := 32; |
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122 | C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF"; |
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123 | C_USE_WSTRB : integer := 0; |
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124 | C_DPHASE_TIMEOUT : integer := 8; |
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125 | C_BASEADDR : std_logic_vector := X"FFFFFFFF"; |
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126 | C_HIGHADDR : std_logic_vector := X"00000000"; |
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127 | C_FAMILY : string := "virtex6"; |
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128 | C_NUM_REG : integer := 1; |
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129 | C_NUM_MEM : integer := 1; |
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130 | C_SLV_AWIDTH : integer := 32; |
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131 | C_SLV_DWIDTH : integer := 32 |
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132 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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133 | ); |
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134 | port |
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135 | ( |
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136 | -- ADD USER PORTS BELOW THIS LINE ------------------ |
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137 | RFA_AD_spi_sclk : out std_logic; |
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138 | RFA_AD_spi_cs_n : out std_logic; |
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139 | RFA_AD_spi_sdio : inout std_logic; |
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140 | RFA_AD_reset_n : out std_logic; |
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141 | |
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142 | RFB_AD_spi_sclk : out std_logic; |
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143 | RFB_AD_spi_cs_n : out std_logic; |
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144 | RFB_AD_spi_sdio : inout std_logic; |
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145 | RFB_AD_reset_n : out std_logic; |
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146 | |
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147 | RFC_AD_spi_sclk : out std_logic; |
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148 | RFC_AD_spi_cs_n : out std_logic; |
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149 | RFC_AD_spi_sdio : inout std_logic; |
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150 | RFC_AD_reset_n : out std_logic; |
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151 | |
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152 | RFD_AD_spi_sclk : out std_logic; |
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153 | RFD_AD_spi_cs_n : out std_logic; |
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154 | RFD_AD_spi_sdio : inout std_logic; |
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155 | RFD_AD_reset_n : out std_logic; |
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156 | |
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157 | RF_AD_TXCLK_out_en : out std_logic; |
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158 | -- ADD USER PORTS ABOVE THIS LINE ------------------ |
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159 | |
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160 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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161 | -- Bus protocol ports, do not add to or delete |
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162 | S_AXI_ACLK : in std_logic; |
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163 | S_AXI_ARESETN : in std_logic; |
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164 | S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); |
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165 | S_AXI_AWVALID : in std_logic; |
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166 | S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); |
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167 | S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); |
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168 | S_AXI_WVALID : in std_logic; |
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169 | S_AXI_BREADY : in std_logic; |
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170 | S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); |
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171 | S_AXI_ARVALID : in std_logic; |
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172 | S_AXI_RREADY : in std_logic; |
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173 | S_AXI_ARREADY : out std_logic; |
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174 | S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); |
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175 | S_AXI_RRESP : out std_logic_vector(1 downto 0); |
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176 | S_AXI_RVALID : out std_logic; |
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177 | S_AXI_WREADY : out std_logic; |
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178 | S_AXI_BRESP : out std_logic_vector(1 downto 0); |
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179 | S_AXI_BVALID : out std_logic; |
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180 | S_AXI_AWREADY : out std_logic |
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181 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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182 | ); |
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183 | |
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184 | attribute MAX_FANOUT : string; |
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185 | attribute SIGIS : string; |
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186 | attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000"; |
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187 | attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000"; |
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188 | attribute SIGIS of S_AXI_ACLK : signal is "Clk"; |
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189 | attribute SIGIS of S_AXI_ARESETN : signal is "Rst"; |
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190 | end entity w3_ad_controller_axi; |
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191 | |
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192 | ------------------------------------------------------------------------------ |
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193 | -- Architecture section |
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194 | ------------------------------------------------------------------------------ |
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195 | |
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196 | architecture IMP of w3_ad_controller_axi is |
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197 | |
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198 | constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; |
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199 | |
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200 | constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; |
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201 | |
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202 | constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); |
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203 | constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; |
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204 | constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; |
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205 | |
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206 | constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := |
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207 | ( |
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208 | ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address |
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209 | ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address |
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210 | ); |
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211 | |
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212 | constant USER_SLV_NUM_REG : integer := 16; |
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213 | constant USER_NUM_REG : integer := USER_SLV_NUM_REG; |
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214 | constant TOTAL_IPIF_CE : integer := USER_NUM_REG; |
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215 | |
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216 | constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := |
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217 | ( |
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218 | 0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space |
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219 | ); |
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220 | |
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221 | ------------------------------------------ |
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222 | -- Index for CS/CE |
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223 | ------------------------------------------ |
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224 | constant USER_SLV_CS_INDEX : integer := 0; |
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225 | constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); |
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226 | |
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227 | constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; |
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228 | |
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229 | ------------------------------------------ |
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230 | -- IP Interconnect (IPIC) signal declarations |
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231 | ------------------------------------------ |
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232 | signal ipif_Bus2IP_Clk : std_logic; |
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233 | signal ipif_Bus2IP_Resetn : std_logic; |
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234 | signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); |
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235 | signal ipif_Bus2IP_RNW : std_logic; |
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236 | signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0); |
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237 | signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0); |
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238 | signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); |
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239 | signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); |
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240 | signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); |
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241 | signal ipif_IP2Bus_WrAck : std_logic; |
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242 | signal ipif_IP2Bus_RdAck : std_logic; |
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243 | signal ipif_IP2Bus_Error : std_logic; |
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244 | signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); |
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245 | signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0); |
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246 | signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0); |
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247 | signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0); |
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248 | signal user_IP2Bus_RdAck : std_logic; |
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249 | signal user_IP2Bus_WrAck : std_logic; |
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250 | signal user_IP2Bus_Error : std_logic; |
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251 | |
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252 | ------------------------------------------ |
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253 | -- Component declaration for verilog user logic |
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254 | ------------------------------------------ |
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255 | component user_logic is |
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256 | generic |
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257 | ( |
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258 | -- ADD USER GENERICS BELOW THIS LINE --------------- |
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259 | INCLUDE_RFC_RFD_IO : integer := 0; |
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260 | -- ADD USER GENERICS ABOVE THIS LINE --------------- |
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261 | |
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262 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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263 | -- Bus protocol parameters, do not add to or delete |
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264 | C_NUM_REG : integer := 16; |
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265 | C_SLV_DWIDTH : integer := 32 |
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266 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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267 | ); |
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268 | port |
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269 | ( |
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270 | -- ADD USER PORTS BELOW THIS LINE ------------------ |
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271 | RFA_AD_spi_sclk : out std_logic; |
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272 | RFA_AD_spi_cs_n : out std_logic; |
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273 | RFA_AD_spi_sdio : inout std_logic; |
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274 | RFA_AD_reset_n : out std_logic; |
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275 | |
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276 | RFB_AD_spi_sclk : out std_logic; |
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277 | RFB_AD_spi_cs_n : out std_logic; |
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278 | RFB_AD_spi_sdio : inout std_logic; |
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279 | RFB_AD_reset_n : out std_logic; |
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280 | |
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281 | RFC_AD_spi_sclk : out std_logic; |
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282 | RFC_AD_spi_cs_n : out std_logic; |
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283 | RFC_AD_spi_sdio : inout std_logic; |
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284 | RFC_AD_reset_n : out std_logic; |
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285 | |
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286 | RFD_AD_spi_sclk : out std_logic; |
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287 | RFD_AD_spi_cs_n : out std_logic; |
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288 | RFD_AD_spi_sdio : inout std_logic; |
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289 | RFD_AD_reset_n : out std_logic; |
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290 | |
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291 | RF_AD_TXCLK_out_en : out std_logic; |
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292 | |
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293 | -- ADD USER PORTS ABOVE THIS LINE ------------------ |
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294 | |
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295 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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296 | -- Bus protocol ports, do not add to or delete |
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297 | Bus2IP_Clk : in std_logic; |
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298 | Bus2IP_Resetn : in std_logic; |
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299 | Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); |
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300 | Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); |
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301 | Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); |
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302 | Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); |
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303 | IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); |
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304 | IP2Bus_RdAck : out std_logic; |
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305 | IP2Bus_WrAck : out std_logic; |
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306 | IP2Bus_Error : out std_logic |
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307 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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308 | ); |
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309 | end component user_logic; |
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310 | |
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311 | begin |
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312 | |
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313 | ------------------------------------------ |
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314 | -- instantiate axi_lite_ipif |
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315 | ------------------------------------------ |
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316 | AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif |
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317 | generic map |
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318 | ( |
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319 | C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH, |
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320 | C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, |
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321 | C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, |
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322 | C_USE_WSTRB => C_USE_WSTRB, |
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323 | C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, |
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324 | C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, |
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325 | C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, |
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326 | C_FAMILY => C_FAMILY |
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327 | ) |
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328 | port map |
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329 | ( |
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330 | S_AXI_ACLK => S_AXI_ACLK, |
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331 | S_AXI_ARESETN => S_AXI_ARESETN, |
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332 | S_AXI_AWADDR => S_AXI_AWADDR, |
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333 | S_AXI_AWVALID => S_AXI_AWVALID, |
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334 | S_AXI_WDATA => S_AXI_WDATA, |
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335 | S_AXI_WSTRB => S_AXI_WSTRB, |
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336 | S_AXI_WVALID => S_AXI_WVALID, |
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337 | S_AXI_BREADY => S_AXI_BREADY, |
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338 | S_AXI_ARADDR => S_AXI_ARADDR, |
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339 | S_AXI_ARVALID => S_AXI_ARVALID, |
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340 | S_AXI_RREADY => S_AXI_RREADY, |
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341 | S_AXI_ARREADY => S_AXI_ARREADY, |
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342 | S_AXI_RDATA => S_AXI_RDATA, |
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343 | S_AXI_RRESP => S_AXI_RRESP, |
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344 | S_AXI_RVALID => S_AXI_RVALID, |
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345 | S_AXI_WREADY => S_AXI_WREADY, |
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346 | S_AXI_BRESP => S_AXI_BRESP, |
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347 | S_AXI_BVALID => S_AXI_BVALID, |
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348 | S_AXI_AWREADY => S_AXI_AWREADY, |
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349 | Bus2IP_Clk => ipif_Bus2IP_Clk, |
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350 | Bus2IP_Resetn => ipif_Bus2IP_Resetn, |
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351 | Bus2IP_Addr => ipif_Bus2IP_Addr, |
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352 | Bus2IP_RNW => ipif_Bus2IP_RNW, |
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353 | Bus2IP_BE => ipif_Bus2IP_BE, |
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354 | Bus2IP_CS => ipif_Bus2IP_CS, |
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355 | Bus2IP_RdCE => ipif_Bus2IP_RdCE, |
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356 | Bus2IP_WrCE => ipif_Bus2IP_WrCE, |
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357 | Bus2IP_Data => ipif_Bus2IP_Data, |
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358 | IP2Bus_WrAck => ipif_IP2Bus_WrAck, |
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359 | IP2Bus_RdAck => ipif_IP2Bus_RdAck, |
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360 | IP2Bus_Error => ipif_IP2Bus_Error, |
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361 | IP2Bus_Data => ipif_IP2Bus_Data |
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362 | ); |
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363 | |
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364 | ------------------------------------------ |
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365 | -- instantiate User Logic |
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366 | ------------------------------------------ |
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367 | USER_LOGIC_I : component user_logic |
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368 | generic map |
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369 | ( |
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370 | -- MAP USER GENERICS BELOW THIS LINE --------------- |
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371 | INCLUDE_RFC_RFD_IO => INCLUDE_RFC_RFD_IO, |
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372 | -- MAP USER GENERICS ABOVE THIS LINE --------------- |
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373 | |
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374 | C_NUM_REG => USER_NUM_REG, |
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375 | C_SLV_DWIDTH => USER_SLV_DWIDTH |
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376 | ) |
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377 | port map |
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378 | ( |
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379 | -- MAP USER PORTS BELOW THIS LINE ------------------ |
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380 | RFA_AD_spi_sclk => RFA_AD_spi_sclk, |
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381 | RFA_AD_spi_cs_n => RFA_AD_spi_cs_n, |
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382 | RFA_AD_spi_sdio => RFA_AD_spi_sdio, |
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383 | RFA_AD_reset_n => RFA_AD_reset_n, |
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384 | |
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385 | RFB_AD_spi_sclk => RFB_AD_spi_sclk, |
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386 | RFB_AD_spi_cs_n => RFB_AD_spi_cs_n, |
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387 | RFB_AD_spi_sdio => RFB_AD_spi_sdio, |
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388 | RFB_AD_reset_n => RFB_AD_reset_n, |
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389 | |
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390 | RFC_AD_spi_sclk => RFC_AD_spi_sclk, |
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391 | RFC_AD_spi_cs_n => RFC_AD_spi_cs_n, |
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392 | RFC_AD_spi_sdio => RFC_AD_spi_sdio, |
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393 | RFC_AD_reset_n => RFC_AD_reset_n, |
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394 | |
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395 | RFD_AD_spi_sclk => RFD_AD_spi_sclk, |
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396 | RFD_AD_spi_cs_n => RFD_AD_spi_cs_n, |
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397 | RFD_AD_spi_sdio => RFD_AD_spi_sdio, |
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398 | RFD_AD_reset_n => RFD_AD_reset_n, |
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399 | RF_AD_TXCLK_out_en => RF_AD_TXCLK_out_en, |
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400 | |
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401 | -- MAP USER PORTS ABOVE THIS LINE ------------------ |
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402 | |
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403 | Bus2IP_Clk => ipif_Bus2IP_Clk, |
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404 | Bus2IP_Resetn => ipif_Bus2IP_Resetn, |
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405 | Bus2IP_Data => ipif_Bus2IP_Data, |
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406 | Bus2IP_BE => ipif_Bus2IP_BE, |
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407 | Bus2IP_RdCE => user_Bus2IP_RdCE, |
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408 | Bus2IP_WrCE => user_Bus2IP_WrCE, |
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409 | IP2Bus_Data => user_IP2Bus_Data, |
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410 | IP2Bus_RdAck => user_IP2Bus_RdAck, |
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411 | IP2Bus_WrAck => user_IP2Bus_WrAck, |
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412 | IP2Bus_Error => user_IP2Bus_Error |
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413 | ); |
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414 | |
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415 | ------------------------------------------ |
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416 | -- connect internal signals |
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417 | ------------------------------------------ |
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418 | ipif_IP2Bus_Data <= user_IP2Bus_Data; |
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419 | ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; |
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420 | ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; |
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421 | ipif_IP2Bus_Error <= user_IP2Bus_Error; |
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422 | |
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423 | user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0); |
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424 | user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0); |
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425 | |
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426 | end IMP; |
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