source: PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/data/w3_clock_controller_axi_v2_1_0.mpd

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##
## Name     : w3_clock_controller_axi
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
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BEGIN w3_clock_controller_axi

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION IP_GROUP = MICROBLAZE:USER
OPTION DESC = W3_CLOCK_CONTROLLER_AXI
OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
OPTION LONG_DESC="Implements SPI master and other logic for configuring the AD9512 clock buffers on the WARP v3 board. This core also supports the CM-MMCX and CM-PLL clock modules for WARP v3."

IO_INTERFACE IO_IF = clk_buffer_SPI, IO_TYPE = W3_CLKCONFIG_V1
IO_INTERFACE IO_IF = usr_gpio, IO_TYPE = W3_CLKCONFIG_V1
IO_INTERFACE IO_IF = at_boot_config, IO_TYPE = W3_CLKCONFIG_V1
IO_INTERFACE IO_IF = clk_mod_IO, IO_TYPE = W3_CLKCONFIG_V1
IO_INTERFACE IO_IF = IIC, IO_TYPE = W3_CLKCONFIG_V1
IO_INTERFACE IO_IF = UART, IO_TYPE = W3_CLKCONFIG_V1

## Bus Interfaces
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
PARAMETER C_USE_WSTRB = 0, DT = INTEGER
PARAMETER C_DPHASE_TIMEOUT = 0, DT = INTEGER
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
PARAMETER C_FAMILY = virtex6, DT = STRING
PARAMETER C_NUM_REG = 1, DT = INTEGER
PARAMETER C_NUM_MEM = 1, DT = INTEGER
PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI

## Ports
PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI

PORT at_boot_clk_in = "", DIR = I, IO_IF=at_boot_config, IO_IS=at_boot_clk
PORT at_boot_clk_in_valid = "", DIR = I, IO_IF=at_boot_config, IO_IS=at_boot_clk_vin
PORT at_boot_config_sw = "", DIR = I, VEC = [2:0], IO_IF=at_boot_config, IO_IS=config_sw
PORT at_boot_clkbuf_clocks_invalid = "", DIR = O, IO_IF=at_boot_config, IO_IS=clocks_invalid

PORT uart_tx = "", DIR = O, IO_IF=UART, IO_IS=uart_tx

PORT iic_eeprom_scl_I = "", DIR =I, IO_IF=IIC, IO_IS=iic_eeprom_scl_I
PORT iic_eeprom_scl_T = "", DIR = O, IO_IF=IIC, IO_IS=iic_eeprom_scl_T
PORT iic_eeprom_scl_O = "", DIR = O, IO_IF=IIC, IO_IS=iic_eeprom_scl_O

PORT iic_eeprom_sda_I = "", DIR =I, IO_IF=IIC, IO_IS=iic_eeprom_sda_I
PORT iic_eeprom_sda_T = "", DIR = O, IO_IF=IIC, IO_IS=iic_eeprom_sda_T
PORT iic_eeprom_sda_O = "", DIR = O, IO_IF=IIC, IO_IS=iic_eeprom_sda_O

PORT samp_spi_sclk = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=sclk
PORT samp_spi_mosi = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=mosi
PORT samp_spi_miso = "", DIR = I, IO_IF=clk_buffer_SPI, IO_IS=miso
PORT samp_spi_cs_n = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=csn
PORT samp_func   = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=func

PORT rfref_spi_sclk = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=sclk
PORT rfref_spi_mosi = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=mosi
PORT rfref_spi_miso = "", DIR = I, IO_IF=clk_buffer_SPI, IO_IS=miso
PORT rfref_spi_cs_n = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=csn
PORT rfref_func  = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=func

PORT cm_spi_sclk = "", DIR = O, IO_IF=clk_mod_IO, IO_IS=sclk
PORT cm_spi_mosi = "", DIR = O, IO_IF=clk_mod_IO, IO_IS=mosi
PORT cm_spi_miso = "", DIR = I, IO_IF=clk_mod_IO, IO_IS=miso
PORT cm_spi_cs_n = "", DIR = O, IO_IF=clk_mod_IO, IO_IS=csn
PORT cm_pll_status = "", DIR = I, IO_IF=clk_mod_IO, IO_IS=pll_status

PORT pll_refclk = "", DIR = I, IO_IF=clk_mod_IO, IO_IS=pll_refclk

PORT usr_reset0 = "", DIR = O, IO_IF=usr_gpio, IO_IS=usr_reset0
PORT usr_reset1 = "", DIR = O, IO_IF=usr_gpio, IO_IS=usr_reset1
PORT usr_reset2 = "", DIR = O, IO_IF=usr_gpio, IO_IS=usr_reset2
PORT usr_reset3 = "", DIR = O, IO_IF=usr_gpio, IO_IS=usr_reset3

PORT usr_status = "", DIR = I, VEC = [31:0], IO_IF=usr_gpio, IO_IS=usr_status

END