| 1 | // |
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| 2 | /////////////////////////////////////////////////////////////////////////////////////////// |
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| 3 | // Copyright © 2011, Xilinx, Inc. |
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| 4 | // This file contains confidential and proprietary information of Xilinx, Inc. and is |
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| 5 | // protected under U.S. and international copyright and other intellectual property laws. |
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| 6 | /////////////////////////////////////////////////////////////////////////////////////////// |
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| 7 | // |
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| 8 | // Disclaimer: |
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| 9 | // This disclaimer is not a license and does not grant any rights to the materials |
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| 10 | // distributed herewith. Except as otherwise provided in a valid license issued to |
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| 11 | // you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE |
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| 12 | // MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY |
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| 13 | // DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, |
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| 14 | // INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, |
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| 15 | // OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable |
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| 16 | // (whether in contract or tort, including negligence, or under any other theory |
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| 17 | // of liability) for any loss or damage of any kind or nature related to, arising |
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| 18 | // under or in connection with these materials, including for any direct, or any |
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| 19 | // indirect, special, incidental, or consequential loss or damage (including loss |
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| 20 | // of data, profits, goodwill, or any type of loss or damage suffered as a result |
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| 21 | // of any action brought by a third party) even if such damage or loss was |
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| 22 | // reasonably foreseeable or Xilinx had been advised of the possibility of the same. |
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| 23 | // |
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| 24 | // CRITICAL APPLICATIONS |
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| 25 | // Xilinx products are not designed or intended to be fail-safe, or for use in any |
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| 26 | // application requiring fail-safe performance, such as life-support or safety |
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| 27 | // devices or systems, Class III medical devices, nuclear facilities, applications |
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| 28 | // related to the deployment of airbags, or any other applications that could lead |
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| 29 | // to death, personal injury, or severe property or environmental damage |
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| 30 | // (individually and collectively, "Critical Applications"). Customer assumes the |
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| 31 | // sole risk and liability of any use of Xilinx products in Critical Applications, |
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| 32 | // subject only to applicable laws and regulations governing limitations on product |
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| 33 | // liability. |
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| 34 | // |
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| 35 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. |
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| 36 | // |
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| 37 | /////////////////////////////////////////////////////////////////////////////////////////// |
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| 38 | // |
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| 39 | // UART Transmitter with integral 16 byte FIFO buffer |
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| 40 | // |
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| 41 | // 8 bit, no parity, 1 stop bit |
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| 42 | // |
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| 43 | // This module was made for use with Spartan-6 Generation Devices and is also ideally |
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| 44 | // suited for use with Virtex-6 and 7-Series devices. |
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| 45 | // |
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| 46 | // Version 1 - 8th July 2011. |
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| 47 | // Derived from uart_tx6.vhd Version 1 (31st March 2011) by Nick Sawyer. |
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| 48 | // |
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| 49 | // Ken Chapman |
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| 50 | // Xilinx Ltd |
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| 51 | // Benchmark House |
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| 52 | // 203 Brooklands Road |
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| 53 | // Weybridge |
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| 54 | // Surrey KT13 ORH |
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| 55 | // United Kingdom |
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| 56 | // |
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| 57 | // chapman@xilinx.com |
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| 58 | // |
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| 59 | /////////////////////////////////////////////////////////////////////////////////////////// |
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| 60 | // |
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| 61 | // Format of this file. |
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| 62 | // |
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| 63 | // The module defines the implementation of the logic using Xilinx primitives. |
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| 64 | // These ensure predictable synthesis results and maximise the density of the |
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| 65 | // implementation. The Unisim Library is used to define Xilinx primitives. It is also |
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| 66 | // used during simulation. |
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| 67 | // The source can be viewed at %XILINX%\verilog\src\unisims\ |
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| 68 | // |
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| 69 | /////////////////////////////////////////////////////////////////////////////////////////// |
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| 70 | // |
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| 71 | |
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| 72 | `timescale 1 ps / 1ps |
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| 73 | |
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| 74 | module uart_tx6 ( |
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| 75 | input [7:0] data_in, |
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| 76 | input buffer_write, |
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| 77 | input buffer_reset, |
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| 78 | input en_16_x_baud, |
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| 79 | output serial_out, |
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| 80 | output buffer_data_present, |
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| 81 | output buffer_half_full, |
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| 82 | output buffer_full, |
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| 83 | input clk ); |
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| 84 | // |
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| 85 | /////////////////////////////////////////////////////////////////////////////////////////// |
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| 86 | // |
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| 87 | // wires used in uart_tx6 |
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| 88 | // |
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| 89 | /////////////////////////////////////////////////////////////////////////////////////////// |
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| 90 | // |
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| 91 | wire [7:0] store_data; |
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| 92 | wire [7:0] data; |
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| 93 | wire [3:0] pointer_value; |
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| 94 | wire [3:0] pointer; |
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| 95 | wire en_pointer; |
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| 96 | wire zero; |
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| 97 | wire full_int; |
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| 98 | wire data_present_value; |
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| 99 | wire data_present_int; |
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| 100 | wire [3:0] sm_value; |
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| 101 | wire [3:0] sm; |
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| 102 | wire [3:0] div_value; |
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| 103 | wire [3:0] div; |
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| 104 | wire lsb_data; |
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| 105 | wire msb_data; |
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| 106 | wire last_bit; |
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| 107 | wire serial_data; |
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| 108 | wire next_value; |
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| 109 | wire next_bit; |
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| 110 | wire buffer_read_value; |
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| 111 | wire buffer_read; |
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| 112 | // |
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| 113 | /////////////////////////////////////////////////////////////////////////////////////////// |
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| 114 | // |
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| 115 | // Start of uart_tx6 circuit description |
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| 116 | // |
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| 117 | /////////////////////////////////////////////////////////////////////////////////////////// |
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| 118 | // |
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| 119 | genvar i; |
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| 120 | |
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| 121 | // SRL16E data storage |
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| 122 | |
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| 123 | generate |
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| 124 | for (i = 0 ; i <= 7 ; i = i+1) |
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| 125 | begin : data_width_loop |
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| 126 | |
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| 127 | (* HBLKNM = "uart_tx6_5" *) |
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| 128 | SRL16E #( |
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| 129 | .INIT (16'h0000)) |
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| 130 | storage_srl ( |
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| 131 | .D (data_in[i]), |
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| 132 | .CE (buffer_write), |
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| 133 | .CLK (clk), |
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| 134 | .A0 (pointer[0]), |
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| 135 | .A1 (pointer[1]), |
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| 136 | .A2 (pointer[2]), |
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| 137 | .A3 (pointer[3]), |
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| 138 | .Q (store_data[i])); |
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| 139 | |
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| 140 | (* HBLKNM = "uart_tx6_5" *) |
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| 141 | FD storage_flop( |
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| 142 | .D (store_data[i]), |
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| 143 | .Q (data[i]), |
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| 144 | .C (clk)); |
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| 145 | |
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| 146 | end //generate data_width_loop; |
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| 147 | endgenerate |
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| 148 | |
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| 149 | (* HBLKNM = "uart_tx6_1" *) |
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| 150 | LUT6 #( |
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| 151 | .INIT (64'hFF00FE00FF80FF00)) |
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| 152 | pointer3_lut( |
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| 153 | .I0 (pointer[0]), |
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| 154 | .I1 (pointer[1]), |
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| 155 | .I2 (pointer[2]), |
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| 156 | .I3 (pointer[3]), |
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| 157 | .I4 (buffer_write), |
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| 158 | .I5 (buffer_read), |
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| 159 | .O (pointer_value[3])); |
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| 160 | |
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| 161 | (* HBLKNM = "uart_tx6_1" *) |
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| 162 | FDR pointer3_flop( |
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| 163 | .D (pointer_value[3]), |
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| 164 | .Q (pointer[3]), |
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| 165 | .R (buffer_reset), |
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| 166 | .C (clk)); |
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| 167 | |
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| 168 | (* HBLKNM = "uart_tx6_1" *) |
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| 169 | LUT6 #( |
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| 170 | .INIT (64'hF0F0E1E0F878F0F0)) |
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| 171 | pointer2_lut( |
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| 172 | .I0 (pointer[0]), |
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| 173 | .I1 (pointer[1]), |
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| 174 | .I2 (pointer[2]), |
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| 175 | .I3 (pointer[3]), |
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| 176 | .I4 (buffer_write), |
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| 177 | .I5 (buffer_read), |
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| 178 | .O (pointer_value[2])); |
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| 179 | |
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| 180 | (* HBLKNM = "uart_tx6_1" *) |
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| 181 | FDR pointer2_flop( |
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| 182 | .D (pointer_value[2]), |
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| 183 | .Q (pointer[2]), |
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| 184 | .R (buffer_reset), |
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| 185 | .C (clk)); |
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| 186 | |
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| 187 | (* HBLKNM = "uart_tx6_1" *) |
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| 188 | LUT6_2 #( |
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| 189 | .INIT (64'hCC9060CCAA5050AA)) |
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| 190 | pointer01_lut( |
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| 191 | .I0 (pointer[0]), |
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| 192 | .I1 (pointer[1]), |
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| 193 | .I2 (en_pointer), |
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| 194 | .I3 (buffer_write), |
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| 195 | .I4 (buffer_read), |
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| 196 | .I5 (1'b1), |
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| 197 | .O5 (pointer_value[0]), |
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| 198 | .O6 (pointer_value[1])); |
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| 199 | |
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| 200 | (* HBLKNM = "uart_tx6_1" *) |
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| 201 | FDR pointer1_flop( |
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| 202 | .D (pointer_value[1]), |
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| 203 | .Q (pointer[1]), |
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| 204 | .R (buffer_reset), |
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| 205 | .C (clk)); |
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| 206 | |
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| 207 | (* HBLKNM = "uart_tx6_1" *) |
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| 208 | FDR pointer0_flop( |
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| 209 | .D (pointer_value[0]), |
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| 210 | .Q (pointer[0]), |
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| 211 | .R (buffer_reset), |
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| 212 | .C (clk)); |
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| 213 | |
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| 214 | (* HBLKNM = "uart_tx6_1" *) |
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| 215 | LUT6_2 #( |
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| 216 | .INIT (64'hF4FCF4FC040004C0)) |
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| 217 | data_present_lut( |
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| 218 | .I0 (zero), |
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| 219 | .I1 (data_present_int), |
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| 220 | .I2 (buffer_write), |
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| 221 | .I3 (buffer_read), |
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| 222 | .I4 (full_int), |
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| 223 | .I5 (1'b1), |
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| 224 | .O5 (en_pointer), |
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| 225 | .O6 (data_present_value)); |
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| 226 | |
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| 227 | (* HBLKNM = "uart_tx6_1" *) |
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| 228 | FDR data_present_flop( |
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| 229 | .D (data_present_value), |
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| 230 | .Q (data_present_int), |
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| 231 | .R (buffer_reset), |
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| 232 | .C (clk)); |
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| 233 | |
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| 234 | (* HBLKNM = "uart_tx6_4" *) |
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| 235 | LUT6_2 #( |
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| 236 | .INIT (64'h0001000080000000)) |
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| 237 | full_lut( |
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| 238 | .I0 (pointer[0]), |
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| 239 | .I1 (pointer[1]), |
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| 240 | .I2 (pointer[2]), |
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| 241 | .I3 (pointer[3]), |
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| 242 | .I4 (1'b1), |
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| 243 | .I5 (1'b1), |
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| 244 | .O5 (full_int), |
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| 245 | .O6 (zero)); |
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| 246 | |
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| 247 | (* HBLKNM = "uart_tx6_4" *) |
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| 248 | LUT6 #( |
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| 249 | .INIT (64'hFF00F0F0CCCCAAAA)) |
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| 250 | lsb_data_lut( |
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| 251 | .I0 (data[0]), |
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| 252 | .I1 (data[1]), |
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| 253 | .I2 (data[2]), |
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| 254 | .I3 (data[3]), |
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| 255 | .I4 (sm[0]), |
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| 256 | .I5 (sm[1]), |
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| 257 | .O (lsb_data)); |
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| 258 | |
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| 259 | (* HBLKNM = "uart_tx6_4" *) |
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| 260 | LUT6 #( |
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| 261 | .INIT (64'hFF00F0F0CCCCAAAA)) |
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| 262 | msb_data_lut( |
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| 263 | .I0 (data[4]), |
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| 264 | .I1 (data[5]), |
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| 265 | .I2 (data[6]), |
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| 266 | .I3 (data[7]), |
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| 267 | .I4 (sm[0]), |
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| 268 | .I5 (sm[1]), |
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| 269 | .O (msb_data)); |
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| 270 | |
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| 271 | (* HBLKNM = "uart_tx6_4" *) |
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| 272 | LUT6_2 #( |
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| 273 | .INIT (64'hCFAACC0F0FFFFFFF)) |
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| 274 | serial_lut( |
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| 275 | .I0 (lsb_data), |
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| 276 | .I1 (msb_data), |
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| 277 | .I2 (sm[1]), |
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| 278 | .I3 (sm[2]), |
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| 279 | .I4 (sm[3]), |
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| 280 | .I5 (1'b1), |
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| 281 | .O5 (last_bit), |
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| 282 | .O6 (serial_data)); |
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| 283 | |
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| 284 | (* HBLKNM = "uart_tx6_4" *) |
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| 285 | FD serial_flop( |
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| 286 | .D (serial_data), |
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| 287 | .Q (serial_out), |
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| 288 | .C (clk)); |
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| 289 | |
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| 290 | (* HBLKNM = "uart_tx6_2" *) |
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| 291 | LUT6 #( |
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| 292 | .INIT (64'h85500000AAAAAAAA)) |
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| 293 | sm0_lut( |
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| 294 | .I0 (sm[0]), |
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| 295 | .I1 (sm[1]), |
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| 296 | .I2 (sm[2]), |
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| 297 | .I3 (sm[3]), |
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| 298 | .I4 (data_present_int), |
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| 299 | .I5 (next_bit), |
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| 300 | .O (sm_value[0])); |
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| 301 | |
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| 302 | (* HBLKNM = "uart_tx6_2" *) |
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| 303 | FD sm0_flop( |
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| 304 | .D (sm_value[0]), |
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| 305 | .Q (sm[0]), |
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| 306 | .C (clk)); |
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| 307 | |
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| 308 | (* HBLKNM = "uart_tx6_2" *) |
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| 309 | LUT6 #( |
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| 310 | .INIT (64'h26610000CCCCCCCC)) |
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| 311 | sm1_lut( |
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| 312 | .I0 (sm[0]), |
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| 313 | .I1 (sm[1]), |
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| 314 | .I2 (sm[2]), |
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| 315 | .I3 (sm[3]), |
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| 316 | .I4 (data_present_int), |
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| 317 | .I5 (next_bit), |
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| 318 | .O (sm_value[1])); |
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| 319 | |
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| 320 | (* HBLKNM = "uart_tx6_2" *) |
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| 321 | FD sm1_flop( |
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| 322 | .D (sm_value[1]), |
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| 323 | .Q (sm[1]), |
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| 324 | .C (clk)); |
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| 325 | |
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| 326 | (* HBLKNM = "uart_tx6_2" *) |
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| 327 | LUT6 #( |
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| 328 | .INIT (64'h88700000F0F0F0F0)) |
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| 329 | sm2_lut( |
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| 330 | .I0 (sm[0]), |
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| 331 | .I1 (sm[1]), |
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| 332 | .I2 (sm[2]), |
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| 333 | .I3 (sm[3]), |
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| 334 | .I4 (data_present_int), |
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| 335 | .I5 (next_bit), |
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| 336 | .O (sm_value[2])); |
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| 337 | |
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| 338 | (* HBLKNM = "uart_tx6_2" *) |
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| 339 | FD sm2_flop( |
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| 340 | .D (sm_value[2]), |
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| 341 | .Q (sm[2]), |
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| 342 | .C (clk)); |
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| 343 | |
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| 344 | (* HBLKNM = "uart_tx6_2" *) |
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| 345 | LUT6 #( |
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| 346 | .INIT (64'h87440000FF00FF00)) |
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| 347 | sm3_lut( |
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| 348 | .I0 (sm[0]), |
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| 349 | .I1 (sm[1]), |
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| 350 | .I2 (sm[2]), |
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| 351 | .I3 (sm[3]), |
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| 352 | .I4 (data_present_int), |
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| 353 | .I5 (next_bit), |
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| 354 | .O (sm_value[3])); |
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| 355 | |
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| 356 | (* HBLKNM = "uart_tx6_2" *) |
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| 357 | FD sm3_flop( |
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| 358 | .D (sm_value[3]), |
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| 359 | .Q (sm[3]), |
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| 360 | .C (clk)); |
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| 361 | |
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| 362 | (* HBLKNM = "uart_tx6_3" *) |
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| 363 | LUT6_2 #( |
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| 364 | .INIT (64'h6C0000005A000000)) |
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| 365 | div01_lut( |
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| 366 | .I0 (div[0]), |
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| 367 | .I1 (div[1]), |
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| 368 | .I2 (en_16_x_baud), |
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| 369 | .I3 (1'b1), |
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| 370 | .I4 (1'b1), |
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| 371 | .I5 (1'b1), |
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| 372 | .O5 (div_value[0]), |
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| 373 | .O6 (div_value[1])); |
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| 374 | |
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| 375 | (* HBLKNM = "uart_tx6_3" *) |
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| 376 | FD div0_flop( |
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| 377 | .D (div_value[0]), |
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| 378 | .Q (div[0]), |
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| 379 | .C (clk)); |
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| 380 | |
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| 381 | (* HBLKNM = "uart_tx6_3" *) |
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| 382 | FD div1_flop( |
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| 383 | .D (div_value[1]), |
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| 384 | .Q (div[1]), |
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| 385 | .C (clk)); |
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| 386 | |
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| 387 | (* HBLKNM = "uart_tx6_3" *) |
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| 388 | LUT6_2 #( |
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| 389 | .INIT (64'h7F80FF007878F0F0)) |
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| 390 | div23_lut( |
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| 391 | .I0 (div[0]), |
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| 392 | .I1 (div[1]), |
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| 393 | .I2 (div[2]), |
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| 394 | .I3 (div[3]), |
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| 395 | .I4 (en_16_x_baud), |
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| 396 | .I5 (1'b1), |
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| 397 | .O5 (div_value[2]), |
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| 398 | .O6 (div_value[3])); |
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| 399 | |
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| 400 | (* HBLKNM = "uart_tx6_3" *) |
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| 401 | FD div2_flop( |
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| 402 | .D (div_value[2]), |
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| 403 | .Q (div[2]), |
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| 404 | .C (clk)); |
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| 405 | |
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| 406 | (* HBLKNM = "uart_tx6_3" *) |
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| 407 | FD div3_flop( |
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| 408 | .D (div_value[3]), |
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| 409 | .Q (div[3]), |
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| 410 | .C (clk)); |
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| 411 | |
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| 412 | (* HBLKNM = "uart_tx6_3" *) |
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| 413 | LUT6_2 #( |
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| 414 | .INIT (64'h0000000080000000)) |
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| 415 | next_lut( |
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| 416 | .I0 (div[0]), |
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| 417 | .I1 (div[1]), |
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| 418 | .I2 (div[2]), |
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| 419 | .I3 (div[3]), |
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| 420 | .I4 (en_16_x_baud), |
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| 421 | .I5 (last_bit), |
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| 422 | .O5 (next_value), |
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| 423 | .O6 (buffer_read_value)); |
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| 424 | |
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| 425 | (* HBLKNM = "uart_tx6_3" *) |
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| 426 | FD next_flop( |
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| 427 | .D (next_value), |
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| 428 | .Q (next_bit), |
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| 429 | .C (clk)); |
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| 430 | |
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| 431 | (* HBLKNM = "uart_tx6_3" *) |
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| 432 | FD read_flop( |
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| 433 | .D (buffer_read_value), |
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| 434 | .Q (buffer_read), |
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| 435 | .C (clk)); |
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| 436 | |
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| 437 | // assign internal wires to outputs |
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| 438 | |
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| 439 | assign buffer_full = full_int; |
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| 440 | assign buffer_half_full = pointer[3]; |
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| 441 | assign buffer_data_present = data_present_int; |
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| 442 | |
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| 443 | endmodule |
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| 444 | |
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| 445 | /////////////////////////////////////////////////////////////////////////////////////////// |
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| 446 | // |
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| 447 | // END OF FILE uart_tx6.v |
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| 448 | // |
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| 449 | /////////////////////////////////////////////////////////////////////////////////////////// |
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| 450 | |
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| 451 | |
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