[4287] | 1 | // |
---|
| 2 | /////////////////////////////////////////////////////////////////////////////////////////// |
---|
| 3 | // Copyright © 2011, Xilinx, Inc. |
---|
| 4 | // This file contains confidential and proprietary information of Xilinx, Inc. and is |
---|
| 5 | // protected under U.S. and international copyright and other intellectual property laws. |
---|
| 6 | /////////////////////////////////////////////////////////////////////////////////////////// |
---|
| 7 | // |
---|
| 8 | // Disclaimer: |
---|
| 9 | // This disclaimer is not a license and does not grant any rights to the materials |
---|
| 10 | // distributed herewith. Except as otherwise provided in a valid license issued to |
---|
| 11 | // you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE |
---|
| 12 | // MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY |
---|
| 13 | // DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, |
---|
| 14 | // INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, |
---|
| 15 | // OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable |
---|
| 16 | // (whether in contract or tort, including negligence, or under any other theory |
---|
| 17 | // of liability) for any loss or damage of any kind or nature related to, arising |
---|
| 18 | // under or in connection with these materials, including for any direct, or any |
---|
| 19 | // indirect, special, incidental, or consequential loss or damage (including loss |
---|
| 20 | // of data, profits, goodwill, or any type of loss or damage suffered as a result |
---|
| 21 | // of any action brought by a third party) even if such damage or loss was |
---|
| 22 | // reasonably foreseeable or Xilinx had been advised of the possibility of the same. |
---|
| 23 | // |
---|
| 24 | // CRITICAL APPLICATIONS |
---|
| 25 | // Xilinx products are not designed or intended to be fail-safe, or for use in any |
---|
| 26 | // application requiring fail-safe performance, such as life-support or safety |
---|
| 27 | // devices or systems, Class III medical devices, nuclear facilities, applications |
---|
| 28 | // related to the deployment of airbags, or any other applications that could lead |
---|
| 29 | // to death, personal injury, or severe property or environmental damage |
---|
| 30 | // (individually and collectively, "Critical Applications"). Customer assumes the |
---|
| 31 | // sole risk and liability of any use of Xilinx products in Critical Applications, |
---|
| 32 | // subject only to applicable laws and regulations governing limitations on product |
---|
| 33 | // liability. |
---|
| 34 | // |
---|
| 35 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. |
---|
| 36 | // |
---|
| 37 | /////////////////////////////////////////////////////////////////////////////////////////// |
---|
| 38 | // |
---|
| 39 | // UART Transmitter with integral 16 byte FIFO buffer |
---|
| 40 | // |
---|
| 41 | // 8 bit, no parity, 1 stop bit |
---|
| 42 | // |
---|
| 43 | // This module was made for use with Spartan-6 Generation Devices and is also ideally |
---|
| 44 | // suited for use with Virtex-6 and 7-Series devices. |
---|
| 45 | // |
---|
| 46 | // Version 1 - 8th July 2011. |
---|
| 47 | // Derived from uart_tx6.vhd Version 1 (31st March 2011) by Nick Sawyer. |
---|
| 48 | // |
---|
| 49 | // Ken Chapman |
---|
| 50 | // Xilinx Ltd |
---|
| 51 | // Benchmark House |
---|
| 52 | // 203 Brooklands Road |
---|
| 53 | // Weybridge |
---|
| 54 | // Surrey KT13 ORH |
---|
| 55 | // United Kingdom |
---|
| 56 | // |
---|
| 57 | // chapman@xilinx.com |
---|
| 58 | // |
---|
| 59 | /////////////////////////////////////////////////////////////////////////////////////////// |
---|
| 60 | // |
---|
| 61 | // Format of this file. |
---|
| 62 | // |
---|
| 63 | // The module defines the implementation of the logic using Xilinx primitives. |
---|
| 64 | // These ensure predictable synthesis results and maximise the density of the |
---|
| 65 | // implementation. The Unisim Library is used to define Xilinx primitives. It is also |
---|
| 66 | // used during simulation. |
---|
| 67 | // The source can be viewed at %XILINX%\verilog\src\unisims\ |
---|
| 68 | // |
---|
| 69 | /////////////////////////////////////////////////////////////////////////////////////////// |
---|
| 70 | // |
---|
| 71 | |
---|
| 72 | `timescale 1 ps / 1ps |
---|
| 73 | |
---|
| 74 | module uart_tx6 ( |
---|
| 75 | input [7:0] data_in, |
---|
| 76 | input buffer_write, |
---|
| 77 | input buffer_reset, |
---|
| 78 | input en_16_x_baud, |
---|
| 79 | output serial_out, |
---|
| 80 | output buffer_data_present, |
---|
| 81 | output buffer_half_full, |
---|
| 82 | output buffer_full, |
---|
| 83 | input clk ); |
---|
| 84 | // |
---|
| 85 | /////////////////////////////////////////////////////////////////////////////////////////// |
---|
| 86 | // |
---|
| 87 | // wires used in uart_tx6 |
---|
| 88 | // |
---|
| 89 | /////////////////////////////////////////////////////////////////////////////////////////// |
---|
| 90 | // |
---|
| 91 | wire [7:0] store_data; |
---|
| 92 | wire [7:0] data; |
---|
| 93 | wire [3:0] pointer_value; |
---|
| 94 | wire [3:0] pointer; |
---|
| 95 | wire en_pointer; |
---|
| 96 | wire zero; |
---|
| 97 | wire full_int; |
---|
| 98 | wire data_present_value; |
---|
| 99 | wire data_present_int; |
---|
| 100 | wire [3:0] sm_value; |
---|
| 101 | wire [3:0] sm; |
---|
| 102 | wire [3:0] div_value; |
---|
| 103 | wire [3:0] div; |
---|
| 104 | wire lsb_data; |
---|
| 105 | wire msb_data; |
---|
| 106 | wire last_bit; |
---|
| 107 | wire serial_data; |
---|
| 108 | wire next_value; |
---|
| 109 | wire next_bit; |
---|
| 110 | wire buffer_read_value; |
---|
| 111 | wire buffer_read; |
---|
| 112 | // |
---|
| 113 | /////////////////////////////////////////////////////////////////////////////////////////// |
---|
| 114 | // |
---|
| 115 | // Start of uart_tx6 circuit description |
---|
| 116 | // |
---|
| 117 | /////////////////////////////////////////////////////////////////////////////////////////// |
---|
| 118 | // |
---|
| 119 | genvar i; |
---|
| 120 | |
---|
| 121 | // SRL16E data storage |
---|
| 122 | |
---|
| 123 | generate |
---|
| 124 | for (i = 0 ; i <= 7 ; i = i+1) |
---|
| 125 | begin : data_width_loop |
---|
| 126 | |
---|
| 127 | (* HBLKNM = "uart_tx6_5" *) |
---|
| 128 | SRL16E #( |
---|
| 129 | .INIT (16'h0000)) |
---|
| 130 | storage_srl ( |
---|
| 131 | .D (data_in[i]), |
---|
| 132 | .CE (buffer_write), |
---|
| 133 | .CLK (clk), |
---|
| 134 | .A0 (pointer[0]), |
---|
| 135 | .A1 (pointer[1]), |
---|
| 136 | .A2 (pointer[2]), |
---|
| 137 | .A3 (pointer[3]), |
---|
| 138 | .Q (store_data[i])); |
---|
| 139 | |
---|
| 140 | (* HBLKNM = "uart_tx6_5" *) |
---|
| 141 | FD storage_flop( |
---|
| 142 | .D (store_data[i]), |
---|
| 143 | .Q (data[i]), |
---|
| 144 | .C (clk)); |
---|
| 145 | |
---|
| 146 | end //generate data_width_loop; |
---|
| 147 | endgenerate |
---|
| 148 | |
---|
| 149 | (* HBLKNM = "uart_tx6_1" *) |
---|
| 150 | LUT6 #( |
---|
| 151 | .INIT (64'hFF00FE00FF80FF00)) |
---|
| 152 | pointer3_lut( |
---|
| 153 | .I0 (pointer[0]), |
---|
| 154 | .I1 (pointer[1]), |
---|
| 155 | .I2 (pointer[2]), |
---|
| 156 | .I3 (pointer[3]), |
---|
| 157 | .I4 (buffer_write), |
---|
| 158 | .I5 (buffer_read), |
---|
| 159 | .O (pointer_value[3])); |
---|
| 160 | |
---|
| 161 | (* HBLKNM = "uart_tx6_1" *) |
---|
| 162 | FDR pointer3_flop( |
---|
| 163 | .D (pointer_value[3]), |
---|
| 164 | .Q (pointer[3]), |
---|
| 165 | .R (buffer_reset), |
---|
| 166 | .C (clk)); |
---|
| 167 | |
---|
| 168 | (* HBLKNM = "uart_tx6_1" *) |
---|
| 169 | LUT6 #( |
---|
| 170 | .INIT (64'hF0F0E1E0F878F0F0)) |
---|
| 171 | pointer2_lut( |
---|
| 172 | .I0 (pointer[0]), |
---|
| 173 | .I1 (pointer[1]), |
---|
| 174 | .I2 (pointer[2]), |
---|
| 175 | .I3 (pointer[3]), |
---|
| 176 | .I4 (buffer_write), |
---|
| 177 | .I5 (buffer_read), |
---|
| 178 | .O (pointer_value[2])); |
---|
| 179 | |
---|
| 180 | (* HBLKNM = "uart_tx6_1" *) |
---|
| 181 | FDR pointer2_flop( |
---|
| 182 | .D (pointer_value[2]), |
---|
| 183 | .Q (pointer[2]), |
---|
| 184 | .R (buffer_reset), |
---|
| 185 | .C (clk)); |
---|
| 186 | |
---|
| 187 | (* HBLKNM = "uart_tx6_1" *) |
---|
| 188 | LUT6_2 #( |
---|
| 189 | .INIT (64'hCC9060CCAA5050AA)) |
---|
| 190 | pointer01_lut( |
---|
| 191 | .I0 (pointer[0]), |
---|
| 192 | .I1 (pointer[1]), |
---|
| 193 | .I2 (en_pointer), |
---|
| 194 | .I3 (buffer_write), |
---|
| 195 | .I4 (buffer_read), |
---|
| 196 | .I5 (1'b1), |
---|
| 197 | .O5 (pointer_value[0]), |
---|
| 198 | .O6 (pointer_value[1])); |
---|
| 199 | |
---|
| 200 | (* HBLKNM = "uart_tx6_1" *) |
---|
| 201 | FDR pointer1_flop( |
---|
| 202 | .D (pointer_value[1]), |
---|
| 203 | .Q (pointer[1]), |
---|
| 204 | .R (buffer_reset), |
---|
| 205 | .C (clk)); |
---|
| 206 | |
---|
| 207 | (* HBLKNM = "uart_tx6_1" *) |
---|
| 208 | FDR pointer0_flop( |
---|
| 209 | .D (pointer_value[0]), |
---|
| 210 | .Q (pointer[0]), |
---|
| 211 | .R (buffer_reset), |
---|
| 212 | .C (clk)); |
---|
| 213 | |
---|
| 214 | (* HBLKNM = "uart_tx6_1" *) |
---|
| 215 | LUT6_2 #( |
---|
| 216 | .INIT (64'hF4FCF4FC040004C0)) |
---|
| 217 | data_present_lut( |
---|
| 218 | .I0 (zero), |
---|
| 219 | .I1 (data_present_int), |
---|
| 220 | .I2 (buffer_write), |
---|
| 221 | .I3 (buffer_read), |
---|
| 222 | .I4 (full_int), |
---|
| 223 | .I5 (1'b1), |
---|
| 224 | .O5 (en_pointer), |
---|
| 225 | .O6 (data_present_value)); |
---|
| 226 | |
---|
| 227 | (* HBLKNM = "uart_tx6_1" *) |
---|
| 228 | FDR data_present_flop( |
---|
| 229 | .D (data_present_value), |
---|
| 230 | .Q (data_present_int), |
---|
| 231 | .R (buffer_reset), |
---|
| 232 | .C (clk)); |
---|
| 233 | |
---|
| 234 | (* HBLKNM = "uart_tx6_4" *) |
---|
| 235 | LUT6_2 #( |
---|
| 236 | .INIT (64'h0001000080000000)) |
---|
| 237 | full_lut( |
---|
| 238 | .I0 (pointer[0]), |
---|
| 239 | .I1 (pointer[1]), |
---|
| 240 | .I2 (pointer[2]), |
---|
| 241 | .I3 (pointer[3]), |
---|
| 242 | .I4 (1'b1), |
---|
| 243 | .I5 (1'b1), |
---|
| 244 | .O5 (full_int), |
---|
| 245 | .O6 (zero)); |
---|
| 246 | |
---|
| 247 | (* HBLKNM = "uart_tx6_4" *) |
---|
| 248 | LUT6 #( |
---|
| 249 | .INIT (64'hFF00F0F0CCCCAAAA)) |
---|
| 250 | lsb_data_lut( |
---|
| 251 | .I0 (data[0]), |
---|
| 252 | .I1 (data[1]), |
---|
| 253 | .I2 (data[2]), |
---|
| 254 | .I3 (data[3]), |
---|
| 255 | .I4 (sm[0]), |
---|
| 256 | .I5 (sm[1]), |
---|
| 257 | .O (lsb_data)); |
---|
| 258 | |
---|
| 259 | (* HBLKNM = "uart_tx6_4" *) |
---|
| 260 | LUT6 #( |
---|
| 261 | .INIT (64'hFF00F0F0CCCCAAAA)) |
---|
| 262 | msb_data_lut( |
---|
| 263 | .I0 (data[4]), |
---|
| 264 | .I1 (data[5]), |
---|
| 265 | .I2 (data[6]), |
---|
| 266 | .I3 (data[7]), |
---|
| 267 | .I4 (sm[0]), |
---|
| 268 | .I5 (sm[1]), |
---|
| 269 | .O (msb_data)); |
---|
| 270 | |
---|
| 271 | (* HBLKNM = "uart_tx6_4" *) |
---|
| 272 | LUT6_2 #( |
---|
| 273 | .INIT (64'hCFAACC0F0FFFFFFF)) |
---|
| 274 | serial_lut( |
---|
| 275 | .I0 (lsb_data), |
---|
| 276 | .I1 (msb_data), |
---|
| 277 | .I2 (sm[1]), |
---|
| 278 | .I3 (sm[2]), |
---|
| 279 | .I4 (sm[3]), |
---|
| 280 | .I5 (1'b1), |
---|
| 281 | .O5 (last_bit), |
---|
| 282 | .O6 (serial_data)); |
---|
| 283 | |
---|
| 284 | (* HBLKNM = "uart_tx6_4" *) |
---|
| 285 | FD serial_flop( |
---|
| 286 | .D (serial_data), |
---|
| 287 | .Q (serial_out), |
---|
| 288 | .C (clk)); |
---|
| 289 | |
---|
| 290 | (* HBLKNM = "uart_tx6_2" *) |
---|
| 291 | LUT6 #( |
---|
| 292 | .INIT (64'h85500000AAAAAAAA)) |
---|
| 293 | sm0_lut( |
---|
| 294 | .I0 (sm[0]), |
---|
| 295 | .I1 (sm[1]), |
---|
| 296 | .I2 (sm[2]), |
---|
| 297 | .I3 (sm[3]), |
---|
| 298 | .I4 (data_present_int), |
---|
| 299 | .I5 (next_bit), |
---|
| 300 | .O (sm_value[0])); |
---|
| 301 | |
---|
| 302 | (* HBLKNM = "uart_tx6_2" *) |
---|
| 303 | FD sm0_flop( |
---|
| 304 | .D (sm_value[0]), |
---|
| 305 | .Q (sm[0]), |
---|
| 306 | .C (clk)); |
---|
| 307 | |
---|
| 308 | (* HBLKNM = "uart_tx6_2" *) |
---|
| 309 | LUT6 #( |
---|
| 310 | .INIT (64'h26610000CCCCCCCC)) |
---|
| 311 | sm1_lut( |
---|
| 312 | .I0 (sm[0]), |
---|
| 313 | .I1 (sm[1]), |
---|
| 314 | .I2 (sm[2]), |
---|
| 315 | .I3 (sm[3]), |
---|
| 316 | .I4 (data_present_int), |
---|
| 317 | .I5 (next_bit), |
---|
| 318 | .O (sm_value[1])); |
---|
| 319 | |
---|
| 320 | (* HBLKNM = "uart_tx6_2" *) |
---|
| 321 | FD sm1_flop( |
---|
| 322 | .D (sm_value[1]), |
---|
| 323 | .Q (sm[1]), |
---|
| 324 | .C (clk)); |
---|
| 325 | |
---|
| 326 | (* HBLKNM = "uart_tx6_2" *) |
---|
| 327 | LUT6 #( |
---|
| 328 | .INIT (64'h88700000F0F0F0F0)) |
---|
| 329 | sm2_lut( |
---|
| 330 | .I0 (sm[0]), |
---|
| 331 | .I1 (sm[1]), |
---|
| 332 | .I2 (sm[2]), |
---|
| 333 | .I3 (sm[3]), |
---|
| 334 | .I4 (data_present_int), |
---|
| 335 | .I5 (next_bit), |
---|
| 336 | .O (sm_value[2])); |
---|
| 337 | |
---|
| 338 | (* HBLKNM = "uart_tx6_2" *) |
---|
| 339 | FD sm2_flop( |
---|
| 340 | .D (sm_value[2]), |
---|
| 341 | .Q (sm[2]), |
---|
| 342 | .C (clk)); |
---|
| 343 | |
---|
| 344 | (* HBLKNM = "uart_tx6_2" *) |
---|
| 345 | LUT6 #( |
---|
| 346 | .INIT (64'h87440000FF00FF00)) |
---|
| 347 | sm3_lut( |
---|
| 348 | .I0 (sm[0]), |
---|
| 349 | .I1 (sm[1]), |
---|
| 350 | .I2 (sm[2]), |
---|
| 351 | .I3 (sm[3]), |
---|
| 352 | .I4 (data_present_int), |
---|
| 353 | .I5 (next_bit), |
---|
| 354 | .O (sm_value[3])); |
---|
| 355 | |
---|
| 356 | (* HBLKNM = "uart_tx6_2" *) |
---|
| 357 | FD sm3_flop( |
---|
| 358 | .D (sm_value[3]), |
---|
| 359 | .Q (sm[3]), |
---|
| 360 | .C (clk)); |
---|
| 361 | |
---|
| 362 | (* HBLKNM = "uart_tx6_3" *) |
---|
| 363 | LUT6_2 #( |
---|
| 364 | .INIT (64'h6C0000005A000000)) |
---|
| 365 | div01_lut( |
---|
| 366 | .I0 (div[0]), |
---|
| 367 | .I1 (div[1]), |
---|
| 368 | .I2 (en_16_x_baud), |
---|
| 369 | .I3 (1'b1), |
---|
| 370 | .I4 (1'b1), |
---|
| 371 | .I5 (1'b1), |
---|
| 372 | .O5 (div_value[0]), |
---|
| 373 | .O6 (div_value[1])); |
---|
| 374 | |
---|
| 375 | (* HBLKNM = "uart_tx6_3" *) |
---|
| 376 | FD div0_flop( |
---|
| 377 | .D (div_value[0]), |
---|
| 378 | .Q (div[0]), |
---|
| 379 | .C (clk)); |
---|
| 380 | |
---|
| 381 | (* HBLKNM = "uart_tx6_3" *) |
---|
| 382 | FD div1_flop( |
---|
| 383 | .D (div_value[1]), |
---|
| 384 | .Q (div[1]), |
---|
| 385 | .C (clk)); |
---|
| 386 | |
---|
| 387 | (* HBLKNM = "uart_tx6_3" *) |
---|
| 388 | LUT6_2 #( |
---|
| 389 | .INIT (64'h7F80FF007878F0F0)) |
---|
| 390 | div23_lut( |
---|
| 391 | .I0 (div[0]), |
---|
| 392 | .I1 (div[1]), |
---|
| 393 | .I2 (div[2]), |
---|
| 394 | .I3 (div[3]), |
---|
| 395 | .I4 (en_16_x_baud), |
---|
| 396 | .I5 (1'b1), |
---|
| 397 | .O5 (div_value[2]), |
---|
| 398 | .O6 (div_value[3])); |
---|
| 399 | |
---|
| 400 | (* HBLKNM = "uart_tx6_3" *) |
---|
| 401 | FD div2_flop( |
---|
| 402 | .D (div_value[2]), |
---|
| 403 | .Q (div[2]), |
---|
| 404 | .C (clk)); |
---|
| 405 | |
---|
| 406 | (* HBLKNM = "uart_tx6_3" *) |
---|
| 407 | FD div3_flop( |
---|
| 408 | .D (div_value[3]), |
---|
| 409 | .Q (div[3]), |
---|
| 410 | .C (clk)); |
---|
| 411 | |
---|
| 412 | (* HBLKNM = "uart_tx6_3" *) |
---|
| 413 | LUT6_2 #( |
---|
| 414 | .INIT (64'h0000000080000000)) |
---|
| 415 | next_lut( |
---|
| 416 | .I0 (div[0]), |
---|
| 417 | .I1 (div[1]), |
---|
| 418 | .I2 (div[2]), |
---|
| 419 | .I3 (div[3]), |
---|
| 420 | .I4 (en_16_x_baud), |
---|
| 421 | .I5 (last_bit), |
---|
| 422 | .O5 (next_value), |
---|
| 423 | .O6 (buffer_read_value)); |
---|
| 424 | |
---|
| 425 | (* HBLKNM = "uart_tx6_3" *) |
---|
| 426 | FD next_flop( |
---|
| 427 | .D (next_value), |
---|
| 428 | .Q (next_bit), |
---|
| 429 | .C (clk)); |
---|
| 430 | |
---|
| 431 | (* HBLKNM = "uart_tx6_3" *) |
---|
| 432 | FD read_flop( |
---|
| 433 | .D (buffer_read_value), |
---|
| 434 | .Q (buffer_read), |
---|
| 435 | .C (clk)); |
---|
| 436 | |
---|
| 437 | // assign internal wires to outputs |
---|
| 438 | |
---|
| 439 | assign buffer_full = full_int; |
---|
| 440 | assign buffer_half_full = pointer[3]; |
---|
| 441 | assign buffer_data_present = data_present_int; |
---|
| 442 | |
---|
| 443 | endmodule |
---|
| 444 | |
---|
| 445 | /////////////////////////////////////////////////////////////////////////////////////////// |
---|
| 446 | // |
---|
| 447 | // END OF FILE uart_tx6.v |
---|
| 448 | // |
---|
| 449 | /////////////////////////////////////////////////////////////////////////////////////////// |
---|
| 450 | |
---|
| 451 | |
---|