source: PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_v3_01_a/data/w3_clock_controller_v2_1_0.mpd

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##
## Name     : warp_clock_controller
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
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BEGIN w3_clock_controller

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION DESC = WARP v3 Clock Buffer Controller
OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
OPTION LONG_DESC="Implements SPI master and other logic for configuring the AD9512 clock buffers on the WARP v3 board"

IO_INTERFACE IO_IF = clk_buffer_SPI, IO_TYPE = W3_CLKCONFIG_V1
IO_INTERFACE IO_IF = usr_gpio, IO_TYPE = W3_CLKCONFIG_V1
IO_INTERFACE IO_IF = at_boot_config, IO_TYPE = W3_CLKCONFIG_V1

## Bus Interfaces
BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
PARAMETER C_INCLUDE_DPHASE_TIMER = 0, DT = INTEGER, RANGE = (0, 1)
PARAMETER C_FAMILY = virtex6, DT = STRING

## Ports
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB


PORT at_boot_clk = "", DIR = I, IO_IF=at_boot_config, IO_IS=at_boot_clk
PORT at_boot_config_sw = "", DIR = I, VEC = [0:1], IO_IF=at_boot_config, IO_IS=config_sw
PORT at_boot_clocks_invalid = "", DIR = O, IO_IF=at_boot_config, IO_IS=clocks_invalid

PORT samp_spi_sclk = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=sclk
PORT samp_spi_mosi = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=mosi
PORT samp_spi_miso = "", DIR = I, IO_IF=clk_buffer_SPI, IO_IS=miso
PORT samp_spi_cs_n = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=csn
PORT samp_func   = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=func

PORT rfref_spi_sclk = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=sclk
PORT rfref_spi_mosi = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=mosi
PORT rfref_spi_miso = "", DIR = I, IO_IF=clk_buffer_SPI, IO_IS=miso
PORT rfref_spi_cs_n = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=csn
PORT rfref_func  = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=func
 
PORT usr_reset0 = "", DIR = O, IO_IF=usr_gpio, IO_IS=usr_reset0
PORT usr_reset1 = "", DIR = O, IO_IF=usr_gpio, IO_IS=usr_reset1
PORT usr_reset2 = "", DIR = O, IO_IF=usr_gpio, IO_IS=usr_reset2
PORT usr_reset3 = "", DIR = O, IO_IF=usr_gpio, IO_IS=usr_reset3

PORT usr_status = "", DIR = I, VEC = [0:31], IO_IF=usr_gpio, IO_IS=usr_status

END