[1766] | 1 | ###################################################################
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| 2 | ##
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| 3 | ## Name : warp_clock_controller
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| 4 | ## Desc : Microprocessor Peripheral Description
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| 5 | ## : Automatically generated by PsfUtility
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| 6 | ##
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| 7 | ###################################################################
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| 8 |
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| 9 | BEGIN w3_clock_controller
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| 10 |
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| 11 | ## Peripheral Options
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| 12 | OPTION IPTYPE = PERIPHERAL
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| 13 | OPTION IMP_NETLIST = TRUE
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| 14 | OPTION HDL = MIXED
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| 15 | OPTION IP_GROUP = MICROBLAZE:PPC:USER
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| 16 | OPTION DESC = WARP v3 Clock Buffer Controller
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| 17 | OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
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| 18 | OPTION LONG_DESC="Implements SPI master and other logic for configuring the AD9512 clock buffers on the WARP v3 board"
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| 19 |
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| 20 | IO_INTERFACE IO_IF = clk_buffer_SPI, IO_TYPE = W3_CLKCONFIG_V1
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| 21 | IO_INTERFACE IO_IF = usr_gpio, IO_TYPE = W3_CLKCONFIG_V1
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[1885] | 22 | IO_INTERFACE IO_IF = at_boot_config, IO_TYPE = W3_CLKCONFIG_V1
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[1766] | 23 |
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| 24 | ## Bus Interfaces
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| 25 | BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
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| 26 |
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| 27 | ## Generics for VHDL or Parameters for Verilog
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| 28 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
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| 29 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
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| 30 | PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
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| 31 | PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
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| 32 | PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
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| 33 | PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
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| 34 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
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| 35 | PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
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| 36 | PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
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| 37 | PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
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| 38 | PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
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| 39 | PARAMETER C_INCLUDE_DPHASE_TIMER = 0, DT = INTEGER, RANGE = (0, 1)
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| 40 | PARAMETER C_FAMILY = virtex6, DT = STRING
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| 41 |
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| 42 | ## Ports
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| 43 | PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
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| 44 | PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
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| 45 | PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
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| 46 | PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
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| 47 | PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
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| 48 | PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
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| 49 | PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
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| 50 | PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
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| 51 | PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
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| 52 | PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
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| 53 | PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
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| 54 | PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
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| 55 | PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
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| 56 | PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
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| 57 | PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
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| 58 | PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
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| 59 | PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
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| 60 | PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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| 61 | PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
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| 62 | PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
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| 63 | PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
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| 64 | PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
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| 65 | PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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| 66 | PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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| 67 | PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
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| 68 | PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
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| 69 | PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
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| 70 | PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
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| 71 | PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
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| 72 | PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
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| 73 | PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
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| 74 | PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
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| 75 | PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
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| 76 | PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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| 77 | PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
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| 78 | PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
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| 79 | PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
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| 80 | PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
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| 81 | PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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| 82 | PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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| 83 | PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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| 84 | PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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| 85 |
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| 86 |
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[1898] | 87 | PORT at_boot_clk = "", DIR = I, IO_IF=at_boot_config, IO_IS=at_boot_clk
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[1885] | 88 | PORT at_boot_config_sw = "", DIR = I, VEC = [0:1], IO_IF=at_boot_config, IO_IS=config_sw
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| 89 | PORT at_boot_clocks_invalid = "", DIR = O, IO_IF=at_boot_config, IO_IS=clocks_invalid
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| 90 |
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[1766] | 91 | PORT samp_spi_sclk = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=sclk
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| 92 | PORT samp_spi_mosi = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=mosi
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| 93 | PORT samp_spi_miso = "", DIR = I, IO_IF=clk_buffer_SPI, IO_IS=miso
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| 94 | PORT samp_spi_cs_n = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=csn
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| 95 | PORT samp_func = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=func
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| 96 |
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| 97 | PORT rfref_spi_sclk = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=sclk
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| 98 | PORT rfref_spi_mosi = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=mosi
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| 99 | PORT rfref_spi_miso = "", DIR = I, IO_IF=clk_buffer_SPI, IO_IS=miso
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| 100 | PORT rfref_spi_cs_n = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=csn
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| 101 | PORT rfref_func = "", DIR = O, IO_IF=clk_buffer_SPI, IO_IS=func
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| 102 |
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| 103 | PORT usr_reset0 = "", DIR = O, IO_IF=usr_gpio, IO_IS=usr_reset0
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| 104 | PORT usr_reset1 = "", DIR = O, IO_IF=usr_gpio, IO_IS=usr_reset1
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| 105 | PORT usr_reset2 = "", DIR = O, IO_IF=usr_gpio, IO_IS=usr_reset2
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| 106 | PORT usr_reset3 = "", DIR = O, IO_IF=usr_gpio, IO_IS=usr_reset3
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| 107 |
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| 108 | PORT usr_status = "", DIR = I, VEC = [0:31], IO_IF=usr_gpio, IO_IS=usr_status
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| 109 |
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| 110 | END
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