source:
PlatformSupport/CustomPeripherals/pcores/w3_iic_eeprom_axi_v1_01_a/hdl/verilog
| Name | Size | Rev | Age | Author | Last Change |
|---|---|---|---|---|---|
| ../ | |||||
| i2c_master_bit_ctrl.v | 20.6 KB | 1927 | 11 years | murphpo | AXI versions of WARP v3 support cores |
| i2c_master_byte_ctrl.v | 10.3 KB | 1927 | 11 years | murphpo | AXI versions of WARP v3 support cores |
| i2c_master_defines.v | 2.9 KB | 1927 | 11 years | murphpo | AXI versions of WARP v3 support cores |
| user_logic.v | 16.0 KB | 4298 | 9 years | murphpo | New boot_io_mux core (muxes IIC/UART between clock config core … |
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