1 | /***************************************************************** |
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2 | * File: w3_iic_eeprom.c |
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3 | * Copyright (c) 2012-2016 Mango Communications, all rights reserved |
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4 | * Released under the WARP License |
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5 | * See http://warp.rice.edu/license for details |
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6 | *****************************************************************/ |
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7 | |
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8 | /** \file w3_iic_eeprom.c |
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9 | |
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10 | \mainpage |
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11 | This is the driver for the w3_iic_eeprom_axi core, which implements an I2C |
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12 | master for accessing the EEPROM on the WARP v3 board. |
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13 | |
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14 | This driver implements functions for reading and writing individual bytes |
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15 | in the EEPROM. Functions are also provided for accessing EEPROM entries |
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16 | written during manufacturing (serial number, etc.). |
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17 | |
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18 | The EEPROM is readable/writable from user-code. However, addresses |
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19 | greater than 16000 are reserved and write-protected. |
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20 | |
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21 | Refer to the <a href="http://warp.rice.edu/trac/wiki/HardwareUsersGuides/WARPv3/EEPROM">WARP v3 User Guide</a> |
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22 | for details on the data written to the EEPROM during manufacturing. |
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23 | |
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24 | To allow the w3_iic_eeprom_axi core to be used as a shared peripheral in |
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25 | a multiple CPU environment, mutex functionality is implemented. The |
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26 | mutex register, IIC_EEPROM_REG_MUTEX, has a special "lock bit" (bit 31) |
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27 | that can lock the ability to update the other bits in the register. The |
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28 | software sequence to use the mutex functionality: |
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29 | - To lock the peripheral: |
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30 | - Write CPU ID and Lock Bit to the mutex register |
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31 | - Read mutex register and check if CPU ID and Lock bit matches |
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32 | - If yes, then CPU has locked the peripheral and can update it |
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33 | - If no, then CPU should not access peripheral |
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34 | |
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35 | - To unlock the peripheral |
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36 | - Write 0 to the mutex register (this will set the lock bit to zero, |
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37 | so the register is writeable again) |
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38 | |
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39 | This approach does not have the unlock protections of the mutex peripheral |
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40 | (i.e. the mutex peripheral uses the CPU ID and potentially the bus master |
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41 | ID to enforce only the CPU who has locked the mutex is unlocking the mutex) |
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42 | but given we are not trying to protect against hacking, the sequence described |
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43 | above should be sufficient to protect the SW driver functions. |
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44 | |
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45 | In order to speed up performance in a multiple CPU environment, when the |
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46 | EEPROM is initialized, it will read all of the defined data values and then |
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47 | cache them into registers within the peripheral. This means that future |
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48 | reads of the defined data values will be much faster, but the initialization |
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49 | of the EEPROM will take longer. The defined data value registers are: |
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50 | IIC_EEPROM_REG_SERIAL_NUM |
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51 | IIC_EEPROM_REG_ETH_A_MAC_ADDR_0 |
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52 | IIC_EEPROM_REG_ETH_A_MAC_ADDR_1 |
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53 | IIC_EEPROM_REG_ETH_B_MAC_ADDR_0 |
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54 | IIC_EEPROM_REG_ETH_B_MAC_ADDR_1 |
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55 | IIC_EEPROM_REG_FPGA_DNA_0 |
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56 | IIC_EEPROM_REG_FPGA_DNA_1 |
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57 | |
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58 | @version 1.02.a |
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59 | @author Patrick Murphy |
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60 | @copyright (c) 2012 Mango Communications, Inc. All rights reserved.<br> |
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61 | Released under the WARP open source license (see http://warp.rice.edu/license) |
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62 | |
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63 | \brief Main source for EEPROM controller driver |
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64 | |
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65 | */ |
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66 | |
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67 | /***************************** Include Files *********************************/ |
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68 | #include "w3_iic_eeprom.h" |
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69 | #include "stdio.h" |
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70 | |
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71 | |
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72 | /*************************** Functions Prototypes ****************************/ |
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73 | |
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74 | inline int iic_eeprom_wait_for_rx_ack(u32 ba); |
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75 | u32 iic_eeprom_read_serial_num(u32 ba); |
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76 | u32 iic_eeprom_read_fpga_dna(u32 ba, int lo_hi); |
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77 | void iic_eeprom_read_eth_addr(u32 ba, u8 addr_sel, u8* addr_buf); |
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78 | int iic_eeprom_write_byte_internal(u32 ba, u16 addr_to_write, u8 byte_to_write); |
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79 | int iic_eeprom_read_byte_internal(u32 ba, u16 addr_to_read); |
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80 | |
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81 | |
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82 | /******************************** Functions **********************************/ |
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83 | |
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84 | |
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85 | /*****************************************************************************/ |
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86 | /** |
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87 | \defgroup user_functions Functions |
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88 | \brief Functions to call from user code |
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89 | \addtogroup user_functions |
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90 | |
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91 | Example: |
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92 | \code{.c} |
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93 | // Assumes user code sets EEPROM_BASEADDR to base address of w3_iic_eeprom |
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94 | // core, as set in xparameters.h |
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95 | |
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96 | int x; |
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97 | u32 board_sn; |
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98 | u32 mutex; |
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99 | |
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100 | // Wait until you lock the EEPROM |
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101 | // In a multiple CPU environment where the EEPROM is a shared |
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102 | // peripheral, the EEPROM mutex must be used for the functions: |
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103 | // - iic_eeprom_init() |
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104 | // - iic_eeprom_write_byte() |
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105 | // - iic_eeprom_read_byte() |
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106 | // since these functions access the I2C bus. All other data access |
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107 | // functions are safe to use without the EEPROM mutex because they |
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108 | // only access registers within the EEPROM peripheral. |
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109 | // |
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110 | do { |
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111 | mutex = iic_eeprom_trylock(EEPROM_BASEADDR, XPAR_CPU_ID); |
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112 | |
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113 | // |
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114 | // Can optionally implement a timeout that will unlock EEPROM. For |
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115 | // reference, the execution time of iic_eeprom_init() is roughly 15 ms on |
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116 | // WARP v3, so any timeout should be much larger than that and greatly |
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117 | // depends on your application. |
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118 | // |
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119 | } while (mutex != IIC_EEPROM_READY); |
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120 | |
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121 | // Initialize the EEPROM controller |
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122 | // - This must be run once before any other EEPROM functions are used |
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123 | iic_eeprom_init(EEPROM_BASEADDR, 0x64); |
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124 | |
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125 | // Write a value to the EEPROM (set EEPROM byte address 2345 to 182) |
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126 | x = iic_eeprom_write_byte(EEPROM_BASEADDR, 2345, 182); |
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127 | if(x != 0) xil_printf("EEPROM Write Error!\n"); |
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128 | |
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129 | // Read the value back from EEPROM |
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130 | x = iic_eeprom_read_byte(EEPROM_BASEADDR, 2345); |
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131 | if(x != 182) xil_printf("EEPROM Read Error (read %d, should be 182)!\n", x); |
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132 | |
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133 | // Unlock the EEPROM |
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134 | iic_eeprom_unlock(EEPROM_BASEADDR); |
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135 | |
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136 | // Read the WARP v3 board serial number from the EEPROM |
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137 | // - Does not need to lock the peripheral using the mutex |
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138 | board_sn = w3_eeprom_read_serial_num(EEPROM_BASEADDDR); |
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139 | xil_printf("Board s/n: W3-a-%05d\n", board_sn); |
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140 | |
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141 | \endcode |
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142 | |
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143 | @{ |
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144 | */ |
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145 | |
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146 | |
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147 | |
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148 | /*****************************************************************************/ |
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149 | /** |
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150 | \brief Initializes the EEPROM controller. This function must be called once at |
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151 | boot before any EEPROM read/write operations. |
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152 | |
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153 | \param ba Base memory address of w3_iic_eeprom pcore |
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154 | \param clk_div Clock divider for IIC clock (set 0x64 for 160MHz bus) |
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155 | \param id CPU ID for mutex lock |
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156 | |
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157 | \returns status: IIC_EEPROM_SUCCESS - EEPROM Initialized |
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158 | IIC_EEPROM_FAILURE - EEPROM not initialized |
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159 | */ |
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160 | int iic_eeprom_init(u32 ba, u8 clk_div, u32 id) { |
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161 | u32 status; |
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162 | u32 tmp; |
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163 | u8 addr_tmp[6]; |
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164 | int mutex; |
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165 | |
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166 | // Is the peripheral initialized |
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167 | status = Xil_In32(ba + IIC_EEPROM_REG_CONFIG_STATUS); |
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168 | |
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169 | if (!(status & IIC_EEPROM_REGMASK_INIT)) { |
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170 | |
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171 | // EEPROM not initialized, try to get a mutex lock |
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172 | mutex = iic_eeprom_trylock(ba, id); |
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173 | |
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174 | if (mutex != IIC_EEPROM_READY) { |
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175 | // Could not get a mutex lock. Return failure. |
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176 | // This condition really means that another CPU is currently |
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177 | // initializing the EEPROM. It should be safe to poll on the |
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178 | // init until it is ready: |
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179 | // |
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180 | // while (iic_eeprom_init() != IIC_EEPROM_SUCCESS) { }; |
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181 | // |
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182 | // since this function will return IIC_EEPROM_SUCCESS immediately |
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183 | // after being initialized. |
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184 | // |
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185 | return IIC_EEPROM_FAILURE; |
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186 | } |
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187 | |
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188 | // Check status again |
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189 | // There is a potential race condition if two CPUs are executing this function: |
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190 | // 1) CPU A reads status NOT_INIT (ie enters code above to try to lock EEPROM) |
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191 | // 2) CPU B writes status INIT (ie has EEPROM lock and has finished init) |
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192 | // 3) CPU B unlocks EEPROM |
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193 | // 4) CPU A executes trylock |
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194 | // |
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195 | // This would cause CPU A to re-initialize the EEPROM even though CPU B |
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196 | // has just finished initializing the EEPROM. Therefore, if we check |
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197 | // one more time here that the EEPROM is truly not initialized, then |
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198 | // there is no more race condition. |
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199 | // |
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200 | status = Xil_In32(ba + IIC_EEPROM_REG_CONFIG_STATUS); |
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201 | |
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202 | if (status & IIC_EEPROM_REGMASK_INIT) { return IIC_EEPROM_SUCCESS; } |
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203 | |
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204 | // Configure the IIC master core |
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205 | Xil_Out32((ba + IIC_EEPROM_REG_CMD), 0); |
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206 | Xil_Out32((ba + IIC_EEPROM_REG_CONFIG_STATUS), (IIC_EEPROM_REGMASK_CLKDIV & clk_div)); |
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207 | Xil_Out32((ba + IIC_EEPROM_REG_CONFIG_STATUS), (Xil_In32(ba + IIC_EEPROM_REG_CONFIG_STATUS) | IIC_EEPROM_REGMASK_CORE_EN)); |
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208 | |
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209 | // Update the cached registers |
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210 | // The serial number should be updated before the MAC addresses because |
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211 | // the MAC addresses potentially use the serial number. |
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212 | // |
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213 | |
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214 | // Serial Number |
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215 | tmp = iic_eeprom_read_serial_num(ba); |
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216 | Xil_Out32((ba + IIC_EEPROM_REG_SERIAL_NUM), tmp); |
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217 | |
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218 | // Ethernet A MAC Address |
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219 | iic_eeprom_read_eth_addr(ba, 0, addr_tmp); |
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220 | |
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221 | tmp = ((addr_tmp[3] << 24) | (addr_tmp[2] << 16) | (addr_tmp[1] << 8) | addr_tmp[0]); |
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222 | Xil_Out32((ba + IIC_EEPROM_REG_ETH_A_MAC_ADDR_0), tmp); |
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223 | |
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224 | tmp = ((addr_tmp[5] << 8) | addr_tmp[4]); |
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225 | Xil_Out32((ba + IIC_EEPROM_REG_ETH_A_MAC_ADDR_1), tmp); |
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226 | |
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227 | // Ethernet B MAC Address |
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228 | iic_eeprom_read_eth_addr(ba, 1, addr_tmp); |
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229 | |
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230 | tmp = ((addr_tmp[3] << 24) | (addr_tmp[2] << 16) | (addr_tmp[1] << 8) | addr_tmp[0]); |
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231 | Xil_Out32((ba + IIC_EEPROM_REG_ETH_B_MAC_ADDR_0), tmp); |
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232 | |
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233 | tmp = ((addr_tmp[5] << 8) | addr_tmp[4]); |
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234 | Xil_Out32((ba + IIC_EEPROM_REG_ETH_B_MAC_ADDR_1), tmp); |
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235 | |
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236 | // FPGA DNA |
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237 | tmp = iic_eeprom_read_fpga_dna(ba, 0); |
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238 | Xil_Out32((ba + IIC_EEPROM_REG_FPGA_DNA_0), tmp); |
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239 | |
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240 | tmp = iic_eeprom_read_fpga_dna(ba, 1); |
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241 | Xil_Out32((ba + IIC_EEPROM_REG_FPGA_DNA_1), tmp); |
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242 | |
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243 | // Set IIC_EEPROM_REGMASK_INIT bit in status register |
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244 | Xil_Out32((ba + IIC_EEPROM_REG_CONFIG_STATUS), (Xil_In32(ba + IIC_EEPROM_REG_CONFIG_STATUS) | IIC_EEPROM_REGMASK_INIT)); |
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245 | |
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246 | // Unlock the EEPROM |
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247 | iic_eeprom_unlock(ba); |
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248 | } |
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249 | |
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250 | return IIC_EEPROM_SUCCESS; |
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251 | } |
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252 | |
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253 | |
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254 | /*****************************************************************************/ |
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255 | /** |
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256 | \brief Try to lock the EEPROM mutex |
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257 | \param ba Base memory address of w3_iic_eeprom pcore |
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258 | \param id ID value to write to the mutex |
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259 | \return Returns IIC_EEPROM_READY or IIC_EEPROM_LOCKED |
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260 | */ |
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261 | int iic_eeprom_trylock(u32 ba, u32 id) { |
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262 | u32 mutex_wr_val; |
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263 | u32 mutex_rd_val; |
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264 | |
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265 | // Set value to write to mutex register |
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266 | mutex_wr_val = (IIC_EEPROM_REGMASK_LOCK | id); |
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267 | |
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268 | // Write mutex register |
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269 | Xil_Out32((ba + IIC_EEPROM_REG_MUTEX), mutex_wr_val); |
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270 | |
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271 | // Read mutex register |
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272 | mutex_rd_val = Xil_In32(ba + IIC_EEPROM_REG_MUTEX); |
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273 | |
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274 | if (mutex_wr_val == mutex_rd_val) { |
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275 | return IIC_EEPROM_READY; |
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276 | } else { |
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277 | return IIC_EEPROM_LOCKED; |
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278 | } |
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279 | } |
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280 | |
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281 | |
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282 | |
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283 | /*****************************************************************************/ |
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284 | /** |
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285 | \brief Unlock the EEPROM mutex |
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286 | \param ba Base memory address of w3_iic_eeprom pcore |
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287 | */ |
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288 | void iic_eeprom_unlock(u32 ba) { |
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289 | // Set mutex register to zero |
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290 | Xil_Out32((ba + IIC_EEPROM_REG_MUTEX), 0); |
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291 | |
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292 | // |
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293 | // By only writing 0 to the mutex register once, this allows the mutex |
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294 | // register to retain the last ID that was used to lock the mutex (ie the |
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295 | // only lock bit is set to zero). This might be useful for debug in the |
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296 | // future and will not affect subsequent writes to the mutex register. |
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297 | // |
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298 | } |
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299 | |
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300 | |
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301 | |
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302 | /*****************************************************************************/ |
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303 | /** |
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304 | \brief Writes one bytes to the EEPROM |
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305 | |
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306 | This method will return IIC_EEPROM_FAILURE if it fails to obtain a mutex lock. |
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307 | It will unlock the mutex after writing the byte. The calling function must |
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308 | check the output value is not IIC_EEPROM_FAILURE before proceeding to write the |
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309 | next byte. |
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310 | |
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311 | NOTE: Addresses greater than 16000 are reserved for manufacturing information. |
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312 | These addresses are not write protected but modifying them can cause issues |
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313 | with the behaviour of the node. |
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314 | |
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315 | \param ba Base memory address of w3_iic_eeprom peripheral |
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316 | \param addr_to_write Byte address to write, in [0,16000] (addresses > 16000 are reserved) |
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317 | \param byte_to_write Byte value to write |
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318 | \return Returns IIC_EEPROM_SUCCESS if EEPROM write succeeds. Returns |
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319 | IIC_EEPROM_FAILURE if an error occurs. |
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320 | */ |
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321 | int iic_eeprom_write_byte(u32 ba, u16 addr_to_write, u8 byte_to_write, u32 id) |
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322 | { |
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323 | int status; |
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324 | int mutex; |
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325 | |
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326 | // Try to get a mutex lock |
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327 | mutex = iic_eeprom_trylock(ba, id); |
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328 | |
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329 | if (mutex != IIC_EEPROM_READY) { |
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330 | // Could not get a mutex lock. Return failure. |
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331 | return IIC_EEPROM_FAILURE; |
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332 | } |
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333 | |
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334 | // Write the byte using the internal method |
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335 | status = iic_eeprom_write_byte_internal(ba, addr_to_write, byte_to_write); |
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336 | |
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337 | // Unlock the EEPROM |
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338 | iic_eeprom_unlock(ba); |
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339 | |
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340 | return status; |
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341 | } |
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342 | |
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343 | |
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344 | |
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345 | /*****************************************************************************/ |
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346 | /** |
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347 | \brief Reads one bytes to the EEPROM |
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348 | |
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349 | This method will return IIC_EEPROM_FAILURE if it fails to obtain a mutex lock. |
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350 | It will unlock the mutex after reading the byte. The calling function must |
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351 | check the output value is not IIC_EEPROM_FAILURE before proceeding to read the |
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352 | next byte. |
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353 | |
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354 | \param ba Base memory address of w3_iic_eeprom peripheral |
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355 | \param addr_to_read Byte address to read (in [0, 16383]) |
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356 | \return If EEPROM read succeeds, the read byte is returned in the LSB. If an |
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357 | error occurs, returns IIC_EEPROM_FAILURE. |
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358 | */ |
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359 | int iic_eeprom_read_byte(u32 ba, u16 addr_to_read, u32 id) |
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360 | { |
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361 | int value; |
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362 | int mutex; |
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363 | |
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364 | // Try to get a mutex lock |
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365 | mutex = iic_eeprom_trylock(ba, id); |
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366 | |
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367 | if (mutex != IIC_EEPROM_READY) { |
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368 | // Could not get a mutex lock. Return failure. |
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369 | return IIC_EEPROM_FAILURE; |
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370 | } |
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371 | |
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372 | // Read the byte using the internal method |
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373 | value = iic_eeprom_read_byte_internal(ba, addr_to_read); |
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374 | |
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375 | // Unlock the EEPROM |
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376 | iic_eeprom_unlock(ba); |
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377 | |
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378 | return value; |
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379 | } |
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380 | |
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381 | |
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382 | |
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383 | /*****************************************************************************/ |
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384 | /** |
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385 | \brief Reads the WARP v3 board serial number (programmed during manufacturing) |
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386 | \param ba Base memory address of w3_iic_eeprom pcore |
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387 | \return Numeric part of board serial number (prefix "W3-a-" not stored in EEPROM) |
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388 | */ |
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389 | u32 w3_eeprom_read_serial_num(u32 ba) |
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390 | { |
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391 | u32 status; |
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392 | |
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393 | status = Xil_In32(ba + IIC_EEPROM_REG_CONFIG_STATUS); |
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394 | |
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395 | if (!(status & IIC_EEPROM_REGMASK_INIT)) { |
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396 | xil_printf("WARNING: EEPROM not initialized\n"); |
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397 | return 0; |
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398 | } |
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399 | |
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400 | return (Xil_In32(ba + IIC_EEPROM_REG_SERIAL_NUM)); |
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401 | } |
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402 | |
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403 | |
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404 | |
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405 | /*****************************************************************************/ |
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406 | /** |
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407 | \brief Reads one of the WARP v3 board Ethernet MAC addresses (programmed during manufacturing) |
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408 | \param ba Base memory address of w3_iic_eeprom pcore |
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409 | \param addr_sel Selection of Ethernet address to retrieve (0=ETH_A address, 1=ETH_B address) |
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410 | \param addr_buf Pointer to array of 6 bytes to store retrieved address. This function will overwrite 6 bytes starting at addr_buf. |
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411 | */ |
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412 | void w3_eeprom_read_eth_addr(u32 ba, u8 addr_sel, u8* addr_buf) |
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413 | { |
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414 | u32 status; |
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415 | u32 tmp_0; |
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416 | u32 tmp_1; |
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417 | |
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418 | // Check that the cached copy has been initialized |
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419 | status = Xil_In32(ba + IIC_EEPROM_REG_CONFIG_STATUS); |
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420 | |
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421 | if (!(status & IIC_EEPROM_REGMASK_INIT)) { |
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422 | xil_printf("WARNING: EEPROM not initialized\n"); |
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423 | |
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424 | // Update the address buffer |
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425 | addr_buf[0] = 0; |
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426 | addr_buf[1] = 0; |
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427 | addr_buf[2] = 0; |
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428 | addr_buf[3] = 0; |
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429 | addr_buf[4] = 0; |
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430 | addr_buf[5] = 0; |
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431 | |
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432 | } else { |
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433 | // Get cached copy of MAC Address |
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434 | if (addr_sel == 0) { |
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435 | // Ethernet A MAC Address |
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436 | tmp_0 = Xil_In32(ba + IIC_EEPROM_REG_ETH_A_MAC_ADDR_0); |
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437 | tmp_1 = Xil_In32(ba + IIC_EEPROM_REG_ETH_A_MAC_ADDR_1); |
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438 | } else { |
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439 | // Ethernet B MAC Address |
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440 | tmp_0 = Xil_In32(ba + IIC_EEPROM_REG_ETH_B_MAC_ADDR_0); |
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441 | tmp_1 = Xil_In32(ba + IIC_EEPROM_REG_ETH_B_MAC_ADDR_1); |
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442 | } |
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443 | |
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444 | // Update the address buffer |
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445 | addr_buf[0] = (tmp_0 & 0x000000FF); |
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446 | addr_buf[1] = (tmp_0 & 0x0000FF00) >> 8; |
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447 | addr_buf[2] = (tmp_0 & 0x00FF0000) >> 16; |
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448 | addr_buf[3] = (tmp_0 & 0xFF000000) >> 24; |
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449 | addr_buf[4] = (tmp_1 & 0x000000FF); |
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450 | addr_buf[5] = (tmp_1 & 0x0000FF00) >> 8; |
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451 | } |
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452 | } |
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453 | |
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454 | |
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455 | |
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456 | /*****************************************************************************/ |
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457 | /** |
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458 | \brief Reads part of the 56-bit Virtex-6 FPGA DNA value (copied to EEPROM during manufacturing) |
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459 | \param ba Base memory address of w3_iic_eeprom pcore |
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460 | \param lo_hi Selects between 32 LSB or 24 MSB of DNA value (0=LSB, 1=MSB) |
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461 | \return Returns selected portion of FPGA DNA value |
---|
462 | */ |
---|
463 | u32 w3_eeprom_read_fpga_dna(u32 ba, int lo_hi) |
---|
464 | { |
---|
465 | u32 status; |
---|
466 | |
---|
467 | // Check that the cached copy has been initialized |
---|
468 | status = Xil_In32(ba + IIC_EEPROM_REG_CONFIG_STATUS); |
---|
469 | |
---|
470 | if (!(status & IIC_EEPROM_REGMASK_INIT)) { |
---|
471 | xil_printf("WARNING: EEPROM not initialized\n"); |
---|
472 | return 0; |
---|
473 | } |
---|
474 | |
---|
475 | // Return cached copy of FPGA DNA |
---|
476 | if (lo_hi == 0) { |
---|
477 | return (Xil_In32(ba + IIC_EEPROM_REG_FPGA_DNA_0)); |
---|
478 | } else { |
---|
479 | return (Xil_In32(ba + IIC_EEPROM_REG_FPGA_DNA_1)); |
---|
480 | } |
---|
481 | } |
---|
482 | |
---|
483 | /** @}*/ //END group user_functions |
---|
484 | |
---|
485 | /// @cond EXCLUDE_FROM_DOCS |
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486 | |
---|
487 | /***************************** Local Functions *******************************/ |
---|
488 | |
---|
489 | /*****************************************************************************/ |
---|
490 | /** |
---|
491 | \brief Reads the WARP v3 board serial number (programmed during manufacturing) |
---|
492 | \param ba Base memory address of w3_iic_eeprom pcore |
---|
493 | \return Numeric part of board serial number (prefix "W3-a-" not stored in EEPROM) |
---|
494 | */ |
---|
495 | u32 iic_eeprom_read_serial_num(u32 ba) |
---|
496 | { |
---|
497 | int x0, x1, x2; |
---|
498 | |
---|
499 | x0 = (int) iic_eeprom_read_byte_internal(ba, 16372); |
---|
500 | x1 = (int) iic_eeprom_read_byte_internal(ba, 16373); |
---|
501 | x2 = (int) iic_eeprom_read_byte_internal(ba, 16374); |
---|
502 | |
---|
503 | return ((x2 << 16) | (x1 << 8) | x0); |
---|
504 | } |
---|
505 | |
---|
506 | |
---|
507 | |
---|
508 | /*****************************************************************************/ |
---|
509 | /** |
---|
510 | \brief Reads one of the WARP v3 board Ethernet MAC addresses (programmed during manufacturing) |
---|
511 | \param ba Base memory address of w3_iic_eeprom pcore |
---|
512 | \param addr_sel Selection of Ethernet address to retrieve (0=ETH_A address, 1=ETH_B address) |
---|
513 | \param addr_buf Pointer to array of 6 bytes to store retrieved address. This function will overwrite 6 bytes starting at addr_buf. |
---|
514 | */ |
---|
515 | void iic_eeprom_read_eth_addr(u32 ba, u8 addr_sel, u8* addr_buf) |
---|
516 | { |
---|
517 | u8 addr_offset; |
---|
518 | u32 sn; |
---|
519 | |
---|
520 | addr_offset = addr_sel ? 6 : 0; |
---|
521 | |
---|
522 | addr_buf[5] = iic_eeprom_read_byte_internal(ba, (16352 + addr_offset)); |
---|
523 | addr_buf[4] = iic_eeprom_read_byte_internal(ba, (16353 + addr_offset)); |
---|
524 | addr_buf[3] = iic_eeprom_read_byte_internal(ba, (16354 + addr_offset)); |
---|
525 | addr_buf[2] = iic_eeprom_read_byte_internal(ba, (16355 + addr_offset)); |
---|
526 | addr_buf[1] = iic_eeprom_read_byte_internal(ba, (16356 + addr_offset)); |
---|
527 | addr_buf[0] = iic_eeprom_read_byte_internal(ba, (16357 + addr_offset)); |
---|
528 | |
---|
529 | if (((addr_buf[0] == 0x40) && (addr_buf[1] == 0xD8) && (addr_buf[2] == 0x55)) == 0) { |
---|
530 | // EEPROM contains invalid (or no) MAC address |
---|
531 | // - Use the node serial number to compute a valid address instead |
---|
532 | // - See http://warpproject.org/trac/wiki/HardwareUsersGuides/WARPv3/Ethernet#MACAddresses |
---|
533 | // |
---|
534 | sn = 2 * Xil_In32(ba + IIC_EEPROM_REG_SERIAL_NUM); |
---|
535 | |
---|
536 | addr_buf[0] = 0x40; |
---|
537 | addr_buf[1] = 0xD8; |
---|
538 | addr_buf[2] = 0x55; |
---|
539 | addr_buf[3] = 0x04; |
---|
540 | addr_buf[4] = 0x20 + ((sn >> 8) & 0xF); |
---|
541 | addr_buf[5] = 0x00 + (sn & 0xFF) + (addr_sel & 0x1); |
---|
542 | } |
---|
543 | |
---|
544 | // If the first three octets match, then the node has a serial number that does not follow the |
---|
545 | // serial_number * 2 scheme. However, we still need to check to make sure that octet [3] and [4] |
---|
546 | // are correct. |
---|
547 | if (addr_buf[3] != 0x04) { // addr_buf[3] must be 0x04 |
---|
548 | addr_buf[3] = 0x04; |
---|
549 | } |
---|
550 | |
---|
551 | if ((addr_buf[4] & 0xF0) != 0x20) { // addr_buf[4] must be 0x2X, where X is in [0..F] |
---|
552 | addr_buf[4] = 0x20 | (addr_buf[4] & 0x0F); |
---|
553 | } |
---|
554 | } |
---|
555 | |
---|
556 | |
---|
557 | |
---|
558 | /*****************************************************************************/ |
---|
559 | /** |
---|
560 | \brief Reads part of the 56-bit Virtex-6 FPGA DNA value (copied to EEPROM during manufacturing) |
---|
561 | \param ba Base memory address of w3_iic_eeprom pcore |
---|
562 | \param lo_hi Selects between 32 LSB or 24 MSB of DNA value (0=LSB, 1=MSB) |
---|
563 | \return Returns selected portion of FPGA DNA value |
---|
564 | */ |
---|
565 | u32 iic_eeprom_read_fpga_dna(u32 ba, int lo_hi) |
---|
566 | { |
---|
567 | int x0, x1, x2, x3; |
---|
568 | |
---|
569 | if (lo_hi == 0) { |
---|
570 | x0 = (int) iic_eeprom_read_byte_internal(ba, 16376); |
---|
571 | x1 = (int) iic_eeprom_read_byte_internal(ba, 16377); |
---|
572 | x2 = (int) iic_eeprom_read_byte_internal(ba, 16378); |
---|
573 | x3 = (int) iic_eeprom_read_byte_internal(ba, 16379); |
---|
574 | |
---|
575 | } else if (lo_hi == 1) { |
---|
576 | x0 = (int) iic_eeprom_read_byte_internal(ba, 16380); |
---|
577 | x1 = (int) iic_eeprom_read_byte_internal(ba, 16381); |
---|
578 | x2 = (int) iic_eeprom_read_byte_internal(ba, 16382); |
---|
579 | x3 = (int) iic_eeprom_read_byte_internal(ba, 16383); |
---|
580 | |
---|
581 | } else { |
---|
582 | return 0; |
---|
583 | } |
---|
584 | |
---|
585 | return ((x3 << 24) | (x2 << 16) | (x1 << 8) | x0); |
---|
586 | } |
---|
587 | |
---|
588 | |
---|
589 | |
---|
590 | /*****************************************************************************/ |
---|
591 | /** |
---|
592 | \brief Writes one bytes to the EEPROM |
---|
593 | |
---|
594 | \param ba Base memory address of w3_iic_eeprom pcore |
---|
595 | \param addr_to_write Byte address to write, in [0,16000] (addresses >16000 are reserved) |
---|
596 | \param byte_to_write Byte value to write |
---|
597 | \return Returns 0 if EEPROM write succeeds. Returns -1 if an error occurs. |
---|
598 | */ |
---|
599 | int iic_eeprom_write_byte_internal(u32 ba, u16 addr_to_write, u8 byte_to_write) |
---|
600 | { |
---|
601 | int write_done; |
---|
602 | |
---|
603 | /* Process to write 1 byte to random address in IIC EEPROM |
---|
604 | - Write EEPROM control word to Tx register {1 0 1 0 0 0 0 RNW}, RNW=0 |
---|
605 | - Assert START and WRITE command bits |
---|
606 | - Poll TIP bit, wait for TIP=0 |
---|
607 | - Read RXACK status bit, should be 0 |
---|
608 | - Write top 8 bits of target address to Tx register |
---|
609 | - Assert WRITE command bit |
---|
610 | - Poll TIP bit, wait for TIP=0 |
---|
611 | - Read RXACK status bit, should be 0 |
---|
612 | - Write bottom 8 bits of target address to Tx register |
---|
613 | - Assert WRITE command bit |
---|
614 | - Poll TIP bit, wait for TIP=0 |
---|
615 | - Read RXACK status bit, should be 0 |
---|
616 | - Write data byte to Tx register |
---|
617 | - Assert STOP and WRITE command bits |
---|
618 | - Poll TIP bit, wait for TIP=0 |
---|
619 | - Read RXACK status bit, should be 0 |
---|
620 | */ |
---|
621 | |
---|
622 | // Protect upper EEPROM bytes |
---|
623 | #if 1 |
---|
624 | if(addr_to_write > 16000) { |
---|
625 | xil_printf("ERROR! High bytes read-only by default. Edit %s to override!\n", __FILE__); |
---|
626 | return IIC_EEPROM_FAILURE; |
---|
627 | } |
---|
628 | #endif |
---|
629 | |
---|
630 | Xil_Out32((ba + IIC_EEPROM_REG_TX), (IIC_EEPROM_CONTROL_WORD_WR)); |
---|
631 | Xil_Out32((ba + IIC_EEPROM_REG_CMD), (IIC_EEPROM_REGMASK_START | IIC_EEPROM_REGMASK_WRITE)); |
---|
632 | if (iic_eeprom_wait_for_rx_ack(ba)) { print("EEPROM: WR Error (1)!\r"); return IIC_EEPROM_FAILURE; } |
---|
633 | |
---|
634 | Xil_Out32((ba + IIC_EEPROM_REG_TX), ((addr_to_write >> 8) & 0xFF)); |
---|
635 | Xil_Out32((ba + IIC_EEPROM_REG_CMD), (IIC_EEPROM_REGMASK_WRITE)); |
---|
636 | if (iic_eeprom_wait_for_rx_ack(ba)) { print("EEPROM: WR Error (2)!\r"); return IIC_EEPROM_FAILURE; } |
---|
637 | |
---|
638 | Xil_Out32((ba + IIC_EEPROM_REG_TX), (addr_to_write & 0xFF)); |
---|
639 | Xil_Out32((ba + IIC_EEPROM_REG_CMD), (IIC_EEPROM_REGMASK_WRITE)); |
---|
640 | if (iic_eeprom_wait_for_rx_ack(ba)) { print("EEPROM: WR Error (3)!\r"); return IIC_EEPROM_FAILURE; } |
---|
641 | |
---|
642 | Xil_Out32((ba + IIC_EEPROM_REG_TX), (byte_to_write & 0xFF)); |
---|
643 | Xil_Out32((ba + IIC_EEPROM_REG_CMD), (IIC_EEPROM_REGMASK_STOP | IIC_EEPROM_REGMASK_WRITE)); |
---|
644 | if (iic_eeprom_wait_for_rx_ack(ba)) { print("EEPROM: WR Error (4)!\r"); return IIC_EEPROM_FAILURE; } |
---|
645 | |
---|
646 | /* Poll the EEPROM until its internal write cycle is complete |
---|
647 | This is done by: |
---|
648 | - Send START |
---|
649 | - Write control word for write command |
---|
650 | - Check for ACK; no ACK means internal write is still ongoing |
---|
651 | */ |
---|
652 | write_done = 0; |
---|
653 | |
---|
654 | while (write_done == 0) |
---|
655 | { |
---|
656 | Xil_Out32((ba + IIC_EEPROM_REG_TX), (IIC_EEPROM_CONTROL_WORD_WR)); |
---|
657 | Xil_Out32((ba + IIC_EEPROM_REG_CMD), (IIC_EEPROM_REGMASK_START | IIC_EEPROM_REGMASK_WRITE)); |
---|
658 | if (iic_eeprom_wait_for_rx_ack(ba) == 0) { write_done = 1; } |
---|
659 | } |
---|
660 | |
---|
661 | return IIC_EEPROM_SUCCESS; |
---|
662 | } |
---|
663 | |
---|
664 | |
---|
665 | |
---|
666 | /*****************************************************************************/ |
---|
667 | /** |
---|
668 | \brief Reads one bytes to the EEPROM |
---|
669 | |
---|
670 | \param ba Base memory address of w3_iic_eeprom pcore |
---|
671 | \param addr_to_read Byte address to read (in [0,16383]) |
---|
672 | \return If EEPROM read succeeds, the read byte is returned in the LSB. If an error occurs, returns -1. |
---|
673 | */ |
---|
674 | int iic_eeprom_read_byte_internal(u32 ba, u16 addr_to_read) |
---|
675 | { |
---|
676 | /* Process to read 1 byte from random address in IIC EEPROM |
---|
677 | - Write EEPROM control word to Tx register {1 0 1 0 0 0 0 RNW}, RNW=0 |
---|
678 | - Assert START and WRITE command bits |
---|
679 | - Poll TIP bit, wait for TIP=0 |
---|
680 | - Read RXACK status bit, should be 0 |
---|
681 | - Write top 8 bits of target address to Tx register |
---|
682 | - Assert WRITE command bit |
---|
683 | - Poll TIP bit, wait for TIP=0 |
---|
684 | - Read RXACK status bit, should be 0 |
---|
685 | - Write bottom 8 bits of target address to Tx register |
---|
686 | - Assert WRITE command bit |
---|
687 | - Poll TIP bit, wait for TIP=0 |
---|
688 | - Read RXACK status bit, should be 0 |
---|
689 | - Write EEPROM control word to Tx register {1 0 1 0 0 0 0 RNW}, RNW=1 |
---|
690 | - Assert START and WRITE command bits (causes repeat START event) |
---|
691 | - Poll TIP bit, wait for TIP=0 |
---|
692 | - Read RXACK status bit, should be 0 |
---|
693 | - Assert STOP, READ and ACK command bits |
---|
694 | - Read received byte from rx register |
---|
695 | */ |
---|
696 | |
---|
697 | Xil_Out32((ba + IIC_EEPROM_REG_TX), (IIC_EEPROM_CONTROL_WORD_WR)); |
---|
698 | Xil_Out32((ba + IIC_EEPROM_REG_CMD), (IIC_EEPROM_REGMASK_START | IIC_EEPROM_REGMASK_WRITE)); |
---|
699 | if (iic_eeprom_wait_for_rx_ack(ba)) { print("EEPROM: RD Error (1)!\r"); return IIC_EEPROM_FAILURE; } |
---|
700 | |
---|
701 | Xil_Out32((ba + IIC_EEPROM_REG_TX), ((addr_to_read >> 8) & 0xFF)); |
---|
702 | Xil_Out32((ba + IIC_EEPROM_REG_CMD), (IIC_EEPROM_REGMASK_WRITE)); |
---|
703 | if (iic_eeprom_wait_for_rx_ack(ba)) { print("EEPROM: RD Error (2)!\r"); return IIC_EEPROM_FAILURE; } |
---|
704 | |
---|
705 | Xil_Out32((ba + IIC_EEPROM_REG_TX), (addr_to_read & 0xFF)); |
---|
706 | Xil_Out32((ba + IIC_EEPROM_REG_CMD), (IIC_EEPROM_REGMASK_WRITE)); |
---|
707 | if (iic_eeprom_wait_for_rx_ack(ba)) { print("EEPROM: RD Error (3)!\r"); return IIC_EEPROM_FAILURE; } |
---|
708 | |
---|
709 | Xil_Out32((ba + IIC_EEPROM_REG_TX), (IIC_EEPROM_CONTROL_WORD_RD)); |
---|
710 | Xil_Out32((ba + IIC_EEPROM_REG_CMD), (IIC_EEPROM_REGMASK_START | IIC_EEPROM_REGMASK_WRITE)); |
---|
711 | if (iic_eeprom_wait_for_rx_ack(ba)) { print("EEPROM: RD Error (4)!\r"); return IIC_EEPROM_FAILURE; } |
---|
712 | |
---|
713 | Xil_Out32((ba + IIC_EEPROM_REG_CMD), (IIC_EEPROM_REGMASK_STOP | IIC_EEPROM_REGMASK_READ | IIC_EEPROM_REGMASK_ACK)); |
---|
714 | while(Xil_In32(ba+IIC_EEPROM_REG_CONFIG_STATUS) & IIC_EEPROM_REGMASK_TIP) {} |
---|
715 | |
---|
716 | return (Xil_In32(ba + IIC_EEPROM_REG_RX) & 0xFF); |
---|
717 | } |
---|
718 | |
---|
719 | |
---|
720 | |
---|
721 | /*****************************************************************************/ |
---|
722 | /** |
---|
723 | \brief Wait for receive acknowledgement |
---|
724 | \param ba Base memory address of w3_iic_eeprom pcore |
---|
725 | \return Returns 0 if IIC bus ACK is detected |
---|
726 | */ |
---|
727 | inline int iic_eeprom_wait_for_rx_ack(u32 ba) |
---|
728 | { |
---|
729 | // xil_printf("Status: 0x%08x CMD: 0x%08x\r", Xil_In32(ba+IIC_EEPROM_REG_CONFIG_STATUS), Xil_In32(ba+IIC_EEPROM_REG_CMD)); |
---|
730 | |
---|
731 | while(Xil_In32(ba+IIC_EEPROM_REG_CONFIG_STATUS) & IIC_EEPROM_REGMASK_TIP) {} |
---|
732 | |
---|
733 | return (0 != (Xil_In32(ba+IIC_EEPROM_REG_CONFIG_STATUS) & IIC_EEPROM_REGMASK_RXACK)); |
---|
734 | } |
---|
735 | |
---|
736 | |
---|
737 | /// @endcond |
---|