[5058] | 1 | /***************************************************************** |
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| 2 | * File: w3_iic_eeprom.h |
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| 3 | * Copyright (c) 2012 Mango Communications, all rights reseved |
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| 4 | * Released under the WARP License |
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| 5 | * See http://warp.rice.edu/license for details |
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| 6 | *****************************************************************/ |
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| 7 | |
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| 8 | /// @cond EXCLUDE_FROM_DOCS |
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| 9 | // User code never uses the #define's from this header, so exclude them from the API docs |
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| 10 | |
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| 11 | #ifndef W3_IIC_EEPROM_H |
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| 12 | #define W3_IIC_EEPROM_H |
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| 13 | |
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| 14 | #include "xil_io.h" |
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| 15 | |
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| 16 | /*************************** Constant Definitions ****************************/ |
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| 17 | |
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| 18 | // -------------------------------------------------------- |
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| 19 | // Address offset for each slave register; exclude from docs, as users never use these directly |
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| 20 | // |
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| 21 | #define W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET (0x00000000) |
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| 22 | #define W3_IIC_EEPROM_SLV_REG_00_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000000) |
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| 23 | #define W3_IIC_EEPROM_SLV_REG_01_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000004) |
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| 24 | #define W3_IIC_EEPROM_SLV_REG_02_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000008) |
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| 25 | #define W3_IIC_EEPROM_SLV_REG_03_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x0000000C) |
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| 26 | #define W3_IIC_EEPROM_SLV_REG_04_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000010) |
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| 27 | #define W3_IIC_EEPROM_SLV_REG_05_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000014) |
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| 28 | #define W3_IIC_EEPROM_SLV_REG_06_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000018) |
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| 29 | #define W3_IIC_EEPROM_SLV_REG_07_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x0000001C) |
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| 30 | #define W3_IIC_EEPROM_SLV_REG_08_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000020) |
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| 31 | #define W3_IIC_EEPROM_SLV_REG_09_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000024) |
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| 32 | #define W3_IIC_EEPROM_SLV_REG_10_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000028) |
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| 33 | #define W3_IIC_EEPROM_SLV_REG_11_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x0000002C) |
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| 34 | #define W3_IIC_EEPROM_SLV_REG_12_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000030) |
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| 35 | #define W3_IIC_EEPROM_SLV_REG_13_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000034) |
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| 36 | #define W3_IIC_EEPROM_SLV_REG_14_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000038) |
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| 37 | #define W3_IIC_EEPROM_SLV_REG_15_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x0000003C) |
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| 38 | |
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| 39 | // -------------------------------------------------------- |
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| 40 | // Register common names |
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| 41 | // |
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| 42 | #define IIC_EEPROM_REG_CONFIG_STATUS W3_IIC_EEPROM_SLV_REG_00_OFFSET |
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| 43 | #define IIC_EEPROM_REG_CMD W3_IIC_EEPROM_SLV_REG_01_OFFSET |
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| 44 | #define IIC_EEPROM_REG_TX W3_IIC_EEPROM_SLV_REG_02_OFFSET |
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| 45 | #define IIC_EEPROM_REG_RX W3_IIC_EEPROM_SLV_REG_03_OFFSET |
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| 46 | #define IIC_EEPROM_REG_MUTEX W3_IIC_EEPROM_SLV_REG_04_OFFSET |
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| 47 | #define IIC_EEPROM_REG_SERIAL_NUM W3_IIC_EEPROM_SLV_REG_05_OFFSET |
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| 48 | #define IIC_EEPROM_REG_ETH_A_MAC_ADDR_0 W3_IIC_EEPROM_SLV_REG_06_OFFSET |
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| 49 | #define IIC_EEPROM_REG_ETH_A_MAC_ADDR_1 W3_IIC_EEPROM_SLV_REG_07_OFFSET |
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| 50 | #define IIC_EEPROM_REG_ETH_B_MAC_ADDR_0 W3_IIC_EEPROM_SLV_REG_08_OFFSET |
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| 51 | #define IIC_EEPROM_REG_ETH_B_MAC_ADDR_1 W3_IIC_EEPROM_SLV_REG_09_OFFSET |
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| 52 | #define IIC_EEPROM_REG_FPGA_DNA_0 W3_IIC_EEPROM_SLV_REG_10_OFFSET |
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| 53 | #define IIC_EEPROM_REG_FPGA_DNA_1 W3_IIC_EEPROM_SLV_REG_11_OFFSET |
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| 54 | |
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| 55 | // -------------------------------------------------------- |
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| 56 | // Masks for config/status register |
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| 57 | // |
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| 58 | #define IIC_EEPROM_REGMASK_CLKDIV 0x000000FF |
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| 59 | #define IIC_EEPROM_REGMASK_CORE_EN 0x00000100 |
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| 60 | #define IIC_EEPROM_REGMASK_RXACK 0x00010000 |
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| 61 | #define IIC_EEPROM_REGMASK_BUSY 0x00020000 |
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| 62 | #define IIC_EEPROM_REGMASK_AL 0x00040000 |
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| 63 | #define IIC_EEPROM_REGMASK_TIP 0x00080000 |
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| 64 | #define IIC_EEPROM_REGMASK_INIT 0x80000000 |
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| 65 | |
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| 66 | // -------------------------------------------------------- |
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| 67 | // Masks for command register |
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| 68 | // |
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| 69 | #define IIC_EEPROM_REGMASK_START 0x00000001 |
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| 70 | #define IIC_EEPROM_REGMASK_STOP 0x00000002 |
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| 71 | #define IIC_EEPROM_REGMASK_READ 0x00000004 |
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| 72 | #define IIC_EEPROM_REGMASK_WRITE 0x00000008 |
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| 73 | #define IIC_EEPROM_REGMASK_ACK 0x00000010 |
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| 74 | |
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| 75 | // -------------------------------------------------------- |
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| 76 | // Masks for mutex register |
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| 77 | // |
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| 78 | #define IIC_EEPROM_REGMASK_LOCK 0x80000000 |
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| 79 | |
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| 80 | #define IIC_EEPROM_READY 0 |
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| 81 | #define IIC_EEPROM_LOCKED 1 |
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| 82 | |
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| 83 | // -------------------------------------------------------- |
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| 84 | // Control Words |
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| 85 | // |
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| 86 | #define IIC_EEPROM_CONTROL_WORD_RD 0xA1 |
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| 87 | #define IIC_EEPROM_CONTROL_WORD_WR 0xA0 |
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| 88 | |
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| 89 | |
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| 90 | // -------------------------------------------------------- |
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[5077] | 91 | // Misc |
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[5058] | 92 | // |
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[5077] | 93 | #define IIC_EEPROM_SUCCESS 0 |
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| 94 | #define IIC_EEPROM_FAILURE -1 |
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| 95 | |
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| 96 | |
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| 97 | // -------------------------------------------------------- |
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| 98 | // Macros (for backward compatibility) |
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| 99 | // |
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| 100 | #define iic_eeprom_readByte(ba, addr) iic_eeprom_read_byte(ba, addr, XPAR_CPU_ID) |
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| 101 | #define iic_eeprom_writeByte(ba, addr, val) iic_eeprom_write_byte(ba, addr, val, XPAR_CPU_ID) |
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[5058] | 102 | #define w3_eeprom_readSerialNum(ba) w3_eeprom_read_serial_num(ba) |
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| 103 | #define w3_eeprom_readEthAddr(ba, sel, buf) w3_eeprom_read_eth_addr(ba, sel, buf) |
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| 104 | |
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| 105 | |
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[5077] | 106 | |
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[5058] | 107 | /*************************** Function Prototypes *****************************/ |
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| 108 | |
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| 109 | // EEPROM functions |
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[5077] | 110 | int iic_eeprom_init(u32 ba, u8 clk_div, u32 id); |
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[5058] | 111 | |
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| 112 | int iic_eeprom_trylock(u32 ba, u32 id); |
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| 113 | void iic_eeprom_unlock(u32 ba); |
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| 114 | |
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[5077] | 115 | int iic_eeprom_write_byte(u32 ba, u16 addr_to_write, u8 byte_to_write, u32 id); |
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| 116 | int iic_eeprom_read_byte(u32 ba, u16 addr_to_read, u32 id); |
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[5058] | 117 | |
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| 118 | // Data access functions |
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| 119 | u32 w3_eeprom_read_serial_num(u32 ba); |
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| 120 | u32 w3_eeprom_read_fpga_dna(u32 ba, int lo_hi); |
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| 121 | void w3_eeprom_read_eth_addr(u32 ba, u8 addr_sel, u8* addr_buf); |
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| 122 | |
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| 123 | #endif /** W3_IIC_EEPROM_H */ |
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| 124 | /// @endcond |
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