1 | #ifndef WARP_SIMPLE_SPI_H |
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2 | #define WARP_SIMPLE_SPI_H |
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3 | |
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4 | #include "xbasic_types.h" |
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5 | #include "xstatus.h" |
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6 | #include "xil_io.h" |
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7 | |
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8 | #define WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET (0x00000000) |
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9 | #define WARP_SIMPLE_SPI_SLV_REG0_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000000) |
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10 | #define WARP_SIMPLE_SPI_SLV_REG1_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000004) |
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11 | #define WARP_SIMPLE_SPI_SLV_REG2_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000008) |
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12 | #define WARP_SIMPLE_SPI_SLV_REG3_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x0000000C) |
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13 | #define WARP_SIMPLE_SPI_SLV_REG4_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000010) |
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14 | #define WARP_SIMPLE_SPI_SLV_REG5_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000014) |
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15 | #define WARP_SIMPLE_SPI_SLV_REG6_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000018) |
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16 | #define WARP_SIMPLE_SPI_SLV_REG7_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x0000001C) |
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17 | #define WARP_SIMPLE_SPI_SLV_REG8_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000020) |
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18 | #define WARP_SIMPLE_SPI_SLV_REG9_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000024) |
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19 | #define WARP_SIMPLE_SPI_SLV_REG10_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000028) |
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20 | #define WARP_SIMPLE_SPI_SLV_REG11_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x0000002C) |
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21 | #define WARP_SIMPLE_SPI_SLV_REG12_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000030) |
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22 | #define WARP_SIMPLE_SPI_SLV_REG13_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000034) |
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23 | #define WARP_SIMPLE_SPI_SLV_REG14_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x00000038) |
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24 | #define WARP_SIMPLE_SPI_SLV_REG15_OFFSET (WARP_SIMPLE_SPI_USER_SLV_SPACE_OFFSET + 0x0000003C) |
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25 | |
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26 | |
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27 | /* Address map: |
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28 | HDL is coded [MSB:LSB] = [31:0] |
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29 | regX[31] maps to 0x80000000 in C driver |
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30 | regX[0] maps to 0x00000001 in C driver |
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31 | |
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32 | 0: Config: |
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33 | [ 3: 0] Clock divider bit sel (00=0.5*busclk, 01=0.25*busclk, ...) 0x0000000F |
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34 | [30:10] Reserved |
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35 | [ 31] Chip select |
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36 | |
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37 | 1: SPI Tx |
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38 | [ 7: 0] Tx data byte |
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39 | [31: 8] Reserved |
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40 | |
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41 | 2: SPI Rx: {samp_rxByte, 24'b0} |
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42 | [ 7: 0] SPI Rx byte |
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43 | [31: 8] Reserved 0xFFFFFF00 |
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44 | |
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45 | 3: FPGA config control: |
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46 | [ 0] SPI Enable (inverted below - reg active high, output active low) - gives FPGA SPI master control of SD card |
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47 | [ 1] Config request (inverted below - reg active high, output active low) - asserting this bit will reconfigure FPGA! |
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48 | [ 7: 2] Reserved |
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49 | [10: 8] Bitstream selection (slot on SD card, [0 to 7]) |
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50 | [31:11] Reserved |
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51 | |
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52 | 4-15: Reserved |
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53 | */ |
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54 | |
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55 | #define SSPI_REG_CONFIG WARP_SIMPLE_SPI_SLV_REG0_OFFSET |
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56 | #define SSPI_REG_SPITX WARP_SIMPLE_SPI_SLV_REG1_OFFSET |
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57 | #define SSPI_REG_SPIRX WARP_SIMPLE_SPI_SLV_REG2_OFFSET |
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58 | #define SSPI_REG_FPGA_CFG_CTRL WARP_SIMPLE_SPI_SLV_REG3_OFFSET |
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59 | |
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60 | #define SSPI_REG_CONFIG_MASK_CLKDIV 0x0000000F |
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61 | #define SSPI_REG_CONFIG_MASK_CS 0x80000000 |
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62 | |
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63 | #define SSPI_REG_FPGA_CFG_MASK_EN 0x00000001 |
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64 | #define SSPI_REG_FPGA_CFG_MASK_GO 0x00000002 |
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65 | #define SSPI_REG_FPGA_CFG_MASK_SLOT 0x00000F00 |
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66 | |
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67 | #define sd_fpga_ctrl_en(ba) Xil_Out32((ba+SSPI_REG_FPGA_CFG_CTRL), (Xil_In32((ba+SSPI_REG_FPGA_CFG_CTRL)) | SSPI_REG_FPGA_CFG_MASK_EN)) |
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68 | #define sd_fpga_ctrl_dis(ba) Xil_Out32((ba+SSPI_REG_FPGA_CFG_CTRL), (Xil_In32((ba+SSPI_REG_FPGA_CFG_CTRL)) & ~SSPI_REG_FPGA_CFG_MASK_EN)) |
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69 | |
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70 | #define sd_config_req(ba) Xil_Out32((ba+SSPI_REG_FPGA_CFG_CTRL), (Xil_In32((ba+SSPI_REG_FPGA_CFG_CTRL)) | SSPI_REG_FPGA_CFG_MASK_GO)) |
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71 | #define sd_config_set_slot(ba, slot) Xil_Out32((ba+SSPI_REG_FPGA_CFG_CTRL), ((Xil_In32((ba+SSPI_REG_FPGA_CFG_CTRL)) & ~SSPI_REG_FPGA_CFG_MASK_SLOT) | (slot&0xF)<<8)) |
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72 | |
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73 | #define simple_spi_set_clkDiv(ba, div) (Xil_Out32((ba+SSPI_REG_CONFIG), \ |
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74 | (Xil_In32((ba+SSPI_REG_CONFIG)) & ~SSPI_REG_CONFIG_MASK_CLKDIV) | (div & SSPI_REG_CONFIG_MASK_CLKDIV))) |
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75 | |
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76 | #define simple_spi_set_cs(ba, cs) (Xil_Out32((ba+SSPI_REG_CONFIG), \ |
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77 | (Xil_In32((ba+SSPI_REG_CONFIG)) & ~SSPI_REG_CONFIG_MASK_CS) | (cs ? SSPI_REG_CONFIG_MASK_CS:0))) |
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78 | |
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79 | //Functions |
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80 | u8 simple_spi_read(u32 baseaddr); |
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81 | void simple_spi_write(u32 baseaddr, u8 txByte); |
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82 | void sd_send_cmd(u32 ba, u8 cmd, u32 args, u8 last_byte); |
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83 | int sd_read_block(u32 ba, u32 blk_offset, u8* buf, u32 blk_size); |
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84 | int sd_write_block(u32 ba, u32 blk_offset, u8* buf, u32 blk_size); |
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85 | int sd_rw_init(u32 ba); |
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86 | |
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87 | #define SD_BLK_SIZE 512 |
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88 | #define SD_BLKS_PER_IMG 18404 //LX240 bitstrem = 9.2MB |
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89 | |
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90 | //Subset of SD card commands for basic init/read/write via SPI |
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91 | #define SD_CMD0 (0x40+0) /* GO_IDLE_STATE */ |
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92 | #define SD_ACMD41 (0x40+41) /* SEND_OP_COND (SDC) */ |
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93 | #define SD_CMD16 (0x40+16) /* SET_BLOCKLEN */ |
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94 | #define SD_CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ |
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95 | #define SD_CMD23 (0x40+23) /* SET_BLOCK_COUNT (MMC) */ |
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96 | #define SD_CMD24 (0x40+24) /* WRITE_BLOCK */ |
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97 | #define SD_CMD55 (0x40+55) /* APP_CMD */ |
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98 | |
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99 | #define SD_DATA_TOKEN_RD 0xFE |
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100 | #define SD_DATA_TOKEN_WR_SINGLE 0xFE |
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101 | #define SD_DATA_TOKEN_WR_MULTI 0xFC |
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102 | #define SD_DATA_TOKEN_STOP_TRAN 0xFD |
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103 | |
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104 | #endif /** WARP_SIMPLE_SPI_H */ |
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