source: PlatformSupport/CustomPeripherals/pcores/w3_userio_axi_v1_00_a/data/w3_userio_axi_v2_1_0.mpd

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##
## Name     : w3_userio_axi
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
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BEGIN w3_userio_axi

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION IP_GROUP = MICROBLAZE:USER
OPTION DESC = W3_USERIO_AXI
OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
OPTION DESC = W3_USERIO
OPTION USAGE_LEVEL = BASE_USER
OPTION DESC = WARP v3 User I/O (AXI)
OPTION LONG_DESC = "Manages interface to all user IO on WARP v3 board. LED outputs can be controlled by software-accessible registers or ports. The control source for each LED is configured independently via a control register. DIP switch and buttons are debounced and captured in a register and driven to output ports."

IO_INTERFACE IO_IF = ext_userio, IO_TYPE = W3_USERIO_V1
IO_INTERFACE IO_IF = user_ports, IO_TYPE = W3_USERIO_V1

## Bus Interfaces
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
PARAMETER C_USE_WSTRB = 0, DT = INTEGER
PARAMETER C_DPHASE_TIMEOUT = 8, DT = INTEGER
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
PARAMETER C_FAMILY = virtex6, DT = STRING
PARAMETER C_NUM_REG = 1, DT = INTEGER
PARAMETER C_NUM_MEM = 1, DT = INTEGER
PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI

PARAMETER HEXDISP_ACTIVE_HIGH = 0, DT = INTEGER, RANGE = (0, 1), VALUES = (0=Active Low, 1=Active High), DESC = "Selects whether hex displays are active high or low on WARP v3 board.", PERMIT = BASE_USER
PARAMETER INCLUDE_DNA_READ_LOGIC = 1, DT = INTEGER, RANGE = (0, 1), VALUES = (0=Do not include DNA read logic, 1=Include DNA read logic), Desc = "Selects whether to include logic to read the Virtex-6 device DNA value. If you use the DNA_PORT primitive elsewhere in the design, it should be excluded here.", PERMIT = BASE_USER

## Ports
PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI

#User ports
PORT hexdisp_left = "", DIR = O, VEC = [0:6], IO_IS = hexdisp_left, IO_IF = ext_userio
PORT hexdisp_right = "", DIR = O, VEC = [0:6], IO_IS = hexdisp_right, IO_IF = ext_userio
PORT hexdisp_left_dp = "", DIR = O, IO_IS = hexdisp_left_dp, IO_IF = ext_userio
PORT hexdisp_right_dp = "", DIR = O, IO_IS = hexdisp_right_dp, IO_IF = ext_userio

PORT leds_red = "", DIR = O, VEC = [0:3], IO_IS = leds_red, IO_IF = ext_userio
PORT leds_green = "", DIR = O, VEC = [0:3], IO_IS = leds_green, IO_IF = ext_userio

PORT rfa_led_red = "", DIR = O, IO_IS = rfa_led_red, IO_IF = ext_userio
PORT rfa_led_green = "", DIR = O, IO_IS = rfa_led_green, IO_IF = ext_userio
PORT rfb_led_red = "", DIR = O, IO_IS = rfb_led_red, IO_IF = ext_userio
PORT rfb_led_green = "", DIR = O, IO_IS = rfb_led_green, IO_IF = ext_userio

PORT dipsw = "", DIR = I, VEC = [0:3], IO_IS = dipsw, IO_IF = ext_userio
PORT pb_u = "", DIR = I, IO_IS = pb_u, IO_IF = ext_userio
PORT pb_m = "", DIR = I, IO_IS = pb_m, IO_IF = ext_userio
PORT pb_d = "", DIR = I, IO_IS = pb_d, IO_IF = ext_userio

PORT usr_hexdisp_left = "", DIR = I, VEC = [0:6], IO_IS = usr_hexdisp_left, IO_IF = user_ports
PORT usr_hexdisp_right = "", DIR = I, VEC = [0:6], IO_IS = usr_hexdisp_right, IO_IF = user_ports
PORT usr_hexdisp_left_dp = "", DIR = I, IO_IS = usr_hexdisp_left_dp, IO_IF = user_ports
PORT usr_hexdisp_right_dp = "", DIR = I, IO_IS = usr_hexdisp_right_dp, IO_IF = user_ports

PORT usr_leds_red = "", DIR = I, VEC = [0:3], IO_IS = usr_leds_red, IO_IF = user_ports
PORT usr_leds_green = "", DIR = I, VEC = [0:3], IO_IS = usr_leds_green, IO_IF = user_ports

PORT usr_rfa_led_red = "", DIR = I, IO_IS = usr_rfa_led_red, IO_IF = user_ports
PORT usr_rfa_led_green = "", DIR = I, IO_IS = usr_rfa_led_green, IO_IF = user_ports
PORT usr_rfb_led_red = "", DIR = I, IO_IS = usr_rfb_led_red, IO_IF = user_ports
PORT usr_rfb_led_green = "", DIR = I, IO_IS = usr_rfb_led_green, IO_IF = user_ports

PORT usr_dipsw = "", DIR = O, VEC = [0:3], IO_IS = usr_dipsw, IO_IF = user_ports
PORT usr_pb_u = "", DIR = O, IO_IS = usr_pb_u, IO_IF = user_ports
PORT usr_pb_m = "", DIR = O, IO_IS = usr_pb_m, IO_IF = user_ports
PORT usr_pb_d = "", DIR = O, IO_IS = usr_pb_d, IO_IF = user_ports

PORT DNA_Port_Clk = "", DIR = I, SIGIS = CLK, CLK_FREQ = 25000000

END