[1927] | 1 | ###################################################################
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| 2 | ##
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| 3 | ## Name : w3_userio_axi
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| 4 | ## Desc : Microprocessor Peripheral Description
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| 5 | ## : Automatically generated by PsfUtility
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| 6 | ##
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| 7 | ###################################################################
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| 8 |
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| 9 | BEGIN w3_userio_axi
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| 10 |
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| 11 | ## Peripheral Options
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| 12 | OPTION IPTYPE = PERIPHERAL
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| 13 | OPTION IMP_NETLIST = TRUE
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| 14 | OPTION HDL = MIXED
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| 15 | OPTION IP_GROUP = MICROBLAZE:USER
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| 16 | OPTION DESC = W3_USERIO_AXI
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| 17 | OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
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| 18 | OPTION DESC = W3_USERIO
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| 19 | OPTION USAGE_LEVEL = BASE_USER
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| 20 | OPTION DESC = WARP v3 User I/O (AXI)
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| 21 | OPTION LONG_DESC = "Manages interface to all user IO on WARP v3 board. LED outputs can be controlled by software-accessible registers or ports. The control source for each LED is configured independently via a control register. DIP switch and buttons are debounced and captured in a register and driven to output ports."
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| 22 |
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| 23 | IO_INTERFACE IO_IF = ext_userio, IO_TYPE = W3_USERIO_V1
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| 24 | IO_INTERFACE IO_IF = user_ports, IO_TYPE = W3_USERIO_V1
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| 25 |
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| 26 | ## Bus Interfaces
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| 27 | BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
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| 28 |
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| 29 | ## Generics for VHDL or Parameters for Verilog
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| 30 | PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
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| 31 | PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
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| 32 | PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
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| 33 | PARAMETER C_USE_WSTRB = 0, DT = INTEGER
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| 34 | PARAMETER C_DPHASE_TIMEOUT = 8, DT = INTEGER
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| 35 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
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| 36 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
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| 37 | PARAMETER C_FAMILY = virtex6, DT = STRING
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| 38 | PARAMETER C_NUM_REG = 1, DT = INTEGER
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| 39 | PARAMETER C_NUM_MEM = 1, DT = INTEGER
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| 40 | PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
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| 41 | PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
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| 42 | PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
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| 43 |
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| 44 | PARAMETER HEXDISP_ACTIVE_HIGH = 0, DT = INTEGER, RANGE = (0, 1), VALUES = (0=Active Low, 1=Active High), DESC = "Selects whether hex displays are active high or low on WARP v3 board.", PERMIT = BASE_USER
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| 45 | PARAMETER INCLUDE_DNA_READ_LOGIC = 1, DT = INTEGER, RANGE = (0, 1), VALUES = (0=Do not include DNA read logic, 1=Include DNA read logic), Desc = "Selects whether to include logic to read the Virtex-6 device DNA value. If you use the DNA_PORT primitive elsewhere in the design, it should be excluded here.", PERMIT = BASE_USER
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| 46 |
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| 47 | ## Ports
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| 48 | PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
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| 49 | PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
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| 50 | PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 51 | PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
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| 52 | PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 53 | PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 54 | PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
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| 55 | PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
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| 56 | PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 57 | PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
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| 58 | PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
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| 59 | PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
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| 60 | PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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| 61 | PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
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| 62 | PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
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| 63 | PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
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| 64 | PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
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| 65 | PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
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| 66 | PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI
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| 67 |
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| 68 | #User ports
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| 69 | PORT hexdisp_left = "", DIR = O, VEC = [0:6], IO_IS = hexdisp_left, IO_IF = ext_userio
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| 70 | PORT hexdisp_right = "", DIR = O, VEC = [0:6], IO_IS = hexdisp_right, IO_IF = ext_userio
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| 71 | PORT hexdisp_left_dp = "", DIR = O, IO_IS = hexdisp_left_dp, IO_IF = ext_userio
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| 72 | PORT hexdisp_right_dp = "", DIR = O, IO_IS = hexdisp_right_dp, IO_IF = ext_userio
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| 73 |
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| 74 | PORT leds_red = "", DIR = O, VEC = [0:3], IO_IS = leds_red, IO_IF = ext_userio
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| 75 | PORT leds_green = "", DIR = O, VEC = [0:3], IO_IS = leds_green, IO_IF = ext_userio
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| 76 |
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| 77 | PORT rfa_led_red = "", DIR = O, IO_IS = rfa_led_red, IO_IF = ext_userio
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| 78 | PORT rfa_led_green = "", DIR = O, IO_IS = rfa_led_green, IO_IF = ext_userio
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| 79 | PORT rfb_led_red = "", DIR = O, IO_IS = rfb_led_red, IO_IF = ext_userio
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| 80 | PORT rfb_led_green = "", DIR = O, IO_IS = rfb_led_green, IO_IF = ext_userio
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| 81 |
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| 82 | PORT dipsw = "", DIR = I, VEC = [0:3], IO_IS = dipsw, IO_IF = ext_userio
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| 83 | PORT pb_u = "", DIR = I, IO_IS = pb_u, IO_IF = ext_userio
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| 84 | PORT pb_m = "", DIR = I, IO_IS = pb_m, IO_IF = ext_userio
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| 85 | PORT pb_d = "", DIR = I, IO_IS = pb_d, IO_IF = ext_userio
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| 86 |
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| 87 | PORT usr_hexdisp_left = "", DIR = I, VEC = [0:6], IO_IS = usr_hexdisp_left, IO_IF = user_ports
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| 88 | PORT usr_hexdisp_right = "", DIR = I, VEC = [0:6], IO_IS = usr_hexdisp_right, IO_IF = user_ports
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| 89 | PORT usr_hexdisp_left_dp = "", DIR = I, IO_IS = usr_hexdisp_left_dp, IO_IF = user_ports
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| 90 | PORT usr_hexdisp_right_dp = "", DIR = I, IO_IS = usr_hexdisp_right_dp, IO_IF = user_ports
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| 91 |
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| 92 | PORT usr_leds_red = "", DIR = I, VEC = [0:3], IO_IS = usr_leds_red, IO_IF = user_ports
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| 93 | PORT usr_leds_green = "", DIR = I, VEC = [0:3], IO_IS = usr_leds_green, IO_IF = user_ports
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| 94 |
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| 95 | PORT usr_rfa_led_red = "", DIR = I, IO_IS = usr_rfa_led_red, IO_IF = user_ports
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| 96 | PORT usr_rfa_led_green = "", DIR = I, IO_IS = usr_rfa_led_green, IO_IF = user_ports
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| 97 | PORT usr_rfb_led_red = "", DIR = I, IO_IS = usr_rfb_led_red, IO_IF = user_ports
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| 98 | PORT usr_rfb_led_green = "", DIR = I, IO_IS = usr_rfb_led_green, IO_IF = user_ports
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| 99 |
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| 100 | PORT usr_dipsw = "", DIR = O, VEC = [0:3], IO_IS = usr_dipsw, IO_IF = user_ports
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| 101 | PORT usr_pb_u = "", DIR = O, IO_IS = usr_pb_u, IO_IF = user_ports
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| 102 | PORT usr_pb_m = "", DIR = O, IO_IS = usr_pb_m, IO_IF = user_ports
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| 103 | PORT usr_pb_d = "", DIR = O, IO_IS = usr_pb_d, IO_IF = user_ports
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| 104 |
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| 105 | PORT DNA_Port_Clk = "", DIR = I, SIGIS = CLK, CLK_FREQ = 25000000
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| 106 |
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| 107 | END
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