source: PlatformSupport/CustomPeripherals/pcores/w3_userio_axi_v1_02_a/src/w3_userio.h

Last change on this file was 5615, checked in by murphpo, 8 years ago

added comments to debug header IO macros
File size: 21.9 KB
Line 
1/*****************************************************************
2* File: w3_userio.h
3* Copyright (c) 2016 Mango Communications, all rights reseved
4* Released under the WARP License
5* See http://warpproject.org/license for details
6*****************************************************************/
7
8/*! \file w3_userio.h
9
10\mainpage
11This is the driver for the w3_userio core, which provides access to all the user IO resources on WARP v3 boards. These resources include
12user LEDs, RF LEDs, hex displays, push buttons and a DIP switch.
13
14This driver only implements macros for reading/writing registers in the w3_userio core hardware. Macros are also provided to read the Virtex-6 device DNA.
15
16@version 1.02.a
17@copyright (c) 2011-2016 Mango Communications, Inc. All rights reserved.<br>
18Released under the WARP open source license (see http://warpproject.org/license)
19
20*/
21    /* Address map:
22        HDL is coded [31:0], adopting Xilinx's convention for AXI IPIF cores
23        All registers are 32-bits
24            regX[31]  maps to 0x80000000 in C driver
25            regX[0]   maps to 0x00000001 in C driver
26
27    0: Control RW
28        [31:30] = Reserved
29        [   29] = Left hex data mode (0=user supplies bit-per-segment; 1=user supplies 4-bit hex)   0x20000000
30        [   28] = Right hex data mode (0=user supplies bit-per-segment; 1=user supplies 4-bit hex)  0x10000000
31      Control source for LEDs: 0=software controlled, 1=usr_ port controlled
32        [27:24] = {rfb_red rfb_green rfa_red rfa_green} 0x0F000000
33        [23:16] = {leds_red leds_green}                 0x00FF0000
34        [15: 8] = {hexdisp_right{a b c d e f g dp}}     0x0000FF00
35        [ 7: 0] = {hexdisp_left{a b c d e f g dp}}      0x000000FF !! Left/Right are swapped in user_logic.v comments
36    1: Left hex display RW
37        [31: 9] = reserved
38        [    8] = DP (controlled directly; doesn't depend on data mode) 0x100
39        [ 6: 0] = Data value ([6:4] ignored when data mode = 1)         0x03F
40    2: Right hex display RW
41        [31: 9] = reserved
42        [    8] = DP (controlled directly; doesn't depend on data mode) 0x100
43        [ 6: 0] = Data value ([6:4] ignored when data mode = 1)         0x03F
44    3: Red user LEDs RW
45        [31: 4] = reserved
46        [ 3: 0] = Data value (1=LED illuminated) 0xF, with 0x1 mapped to lowest LED
47    4: Green user LEDs RW
48        [31: 4] = reserved
49        [ 3: 0] = Data value (1=LED illuminated) 0xF, with 0x1 mapped to lowest LED
50    5: RF LEDs RW
51        [31: 4] = reserved
52        [    3] = rfb_red   0x8
53        [    2] = rfb_green 0x4
54        [    1] = rfa_red   0x2
55        [    0] = rfa_green 0x1
56    6: Switch/button inputs RO
57        [31: 7] = reserved
58        [    6] = pb_up         0x40
59        [    5] = pb_mid        0x20
60        [    4] = pb_down       0x10
61        [ 3: 0] = DIP switch    0x0F (with 0x1 mapped to right-most switch)
62
63    7: PWM Gen Param: PWM period RW
64        [31:29] = reserved
65        [28: 0] = PWN period
66
67    8: PWM Gen Param: PWM output deassert thresh RW
68        [31:29] = reserved
69        [28: 0] = PWM output deassert thresh
70       
71    9: PWM Gen Param: PWM ramp step RW
72        [31]    = ramp enabled
73        [30:20] = reserved
74        [19: 0] = PWM thresh ramp step
75
76    10: HW Output control sel RW
77        [31:28] = Reserved
78      HW Control source for LEDs: 0=usr_ ports, 1=pwm gen (same ctrlSrc masks as reg0)
79        [27:24] = {rfb_red rfb_green rfa_red rfa_green} 0x0F000000
80        [23:16] = {leds_red leds_green}                 0x00FF0000
81        [15: 8] = {hexdisp_left{a b c d e f g dp}}      0x0000FF00
82        [ 7: 0] = {hexdisp_right{a b c d e f g dp}}     0x000000FF
83
84    11: FPGA DNA LSB
85        [31: 0] = 32LSB of FPGA DNA
86
87    12: FPGA DNA MSB
88        [31:25] = reserved
89        [24: 0] = FPGA DNA 25MSB
90
91    13: Debug Header IO
92        [31:16] = IOB direction control, 1 bit per pin; only C_DBG_HDR_WIDTH LSB are used
93        [15: 0] = IOB data. Bits corresponding to inputs contain input values. Bits
94                   corresponding to outputs contain output values. Bits corresponding to
95                   unused pins contain would-be output values (whatever software last wrote).
96        */
97
98#ifndef W3_USERIO_H
99#define W3_USERIO_H
100
101#include "xil_io.h"
102
103/// @cond EXCLUDE_FROM_DOCS
104// Address offset for each slave register; exclude from docs, as users never use these directly
105#define W3_USERIO_USER_SLV_SPACE_OFFSET (0x00000000)
106#define W3_USERIO_SLV_REG0_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000000)
107#define W3_USERIO_SLV_REG1_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000004)
108#define W3_USERIO_SLV_REG2_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000008)
109#define W3_USERIO_SLV_REG3_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x0000000C)
110#define W3_USERIO_SLV_REG4_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000010)
111#define W3_USERIO_SLV_REG5_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000014)
112#define W3_USERIO_SLV_REG6_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000018)
113#define W3_USERIO_SLV_REG7_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x0000001C)
114#define W3_USERIO_SLV_REG8_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000020)
115#define W3_USERIO_SLV_REG9_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000024)
116#define W3_USERIO_SLV_REG10_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000028)
117#define W3_USERIO_SLV_REG11_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x0000002C)
118#define W3_USERIO_SLV_REG12_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000030)
119#define W3_USERIO_SLV_REG13_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000034)
120/// @endcond
121
122/** \defgroup control_reg Control registers
123 *  \addtogroup control_reg
124<b>Hardware vs. software control</b>:
125Every LED and hex display segment can be controlled either via software or hardware:
126<ul>
127<li><b>Software</b>: user code sets LED state by writing a 1 to the corresponding register bit
128<li><b>Hardware</b>: Two modes:<ul>
129   <li><b>Port mode</b>: LED state is controlled by corresponding usr_* port
130   <li><b>PWM mode</b>:  LED state is controlled by internal PWM waveform generator
131   </ul>
132</ul>
133
134The WARP reference designs use hardware/port control for the RF LEDs (to indicate real-time Tx/Rx state of each RF interface) and software control
135for all other LED/hex display outputs.
136
137The control source (hw or sw) for each output bit is set by the control register described below.
138
139Examples:
140\code{.c}
141//Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h
142
143//------------------------------------------------------------------------------
144// Set both hex dipslays to map 4-bit to 7-segment values automatically
145userio_write_control(USERIO_BASEADDR, (W3_USERIO_HEXDISP_L_MAPMODE | W3_USERIO_HEXDISP_R_MAPMODE));
146
147//------------------------------------------------------------------------------
148// Select software control of all outputs
149userio_set_ctrlSrc_sw(USERIO_BASEADDR, (W3_USERIO_CTRLSRC_LEDS_RF | W3_USERIO_CTRLSRC_LEDS | W3_USERIO_CTRLSRC_HEXDISPS));
150
151//------------------------------------------------------------------------------
152// Select hardware/port control of RF LEDs
153userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RF);
154
155//------------------------------------------------------------------------------
156// Enable hardware control of green user LEDs, software control of red user LEDs
157userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_GREEN);
158userio_set_ctrlSrc_sw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED);
159
160//------------------------------------------------------------------------------
161// Use the PWM generator to slowly blink the green LEDs
162userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_GREEN);
163userio_set_hw_ctrl_mode_pwm(USERIO_BASEADDR, (W3_USERIO_CTRLSRC_LEDS_GREEN);
164userio_set_pwm_ramp_en(USERIO_BASEADDR, 0);
165userio_set_pwm_period(USERIO_BASEADDR, 65530);
166userio_set_pwm_thresh(USERIO_BASEADDR, 65530/2);
167
168//------------------------------------------------------------------------------
169// Use the PWM generator to show a "sleep" pattern on red LEDs
170userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED);
171userio_set_hw_ctrl_mode_pwm(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED);
172
173//Use fast period so blinking is not visable
174// (fast blink with low duty cycle looks like a dim constant brightness)
175userio_set_pwm_period(USERIO_BASEADDR, 500);
176
177//Ramp must be disabled when changing ramp params
178userio_set_pwm_ramp_en(USERIO_BASEADDR, 0);
179userio_set_pwm_ramp_min(USERIO_BASEADDR, 2);
180userio_set_pwm_ramp_max(USERIO_BASEADDR, 250);
181userio_set_pwm_ramp_en(USERIO_BASEADDR, 1);
182\endcode
183
184 * @{
185 */
186
187#define userio_read_control(baseaddr)       Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) //!< Returns the value of the control register
188#define userio_write_control(baseaddr, x)       Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, x) //!< Sets the control register to x
189
190#define userio_set_ctrlSrc_sw(baseaddr, ioMask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) & ~(ioMask)))//!< Sets selected outputs to software control (register writes)
191#define userio_set_ctrlSrc_hw(baseaddr, ioMask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) | (ioMask))) //!< Sets selected outputs to hardware control (usr_ ports)
192
193#define userio_set_hw_ctrl_mode_pwm(baseaddr, ioMask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG10_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG10_OFFSET) | (ioMask))) //!< Sets selected outputs to use PWM generator for hardware/PWM control
194#define userio_set_hw_ctrl_mode_port(baseaddr, ioMask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG10_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG10_OFFSET) & (~ioMask))) //!< Sets selected outputs to use PWM generator for hardware/port control
195
196//PWM config macros
197#define userio_set_pwm_period(baseaddr, p) Xil_Out32(baseaddr+W3_USERIO_SLV_REG7_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG7_OFFSET) & 0x0000FFFF) | (((p) & 0xFFFF)<<16)) //!< Sets the PWM period; larger periods result in slower blinking
198#define userio_set_pwm_thresh(baseaddr, t) Xil_Out32(baseaddr+W3_USERIO_SLV_REG7_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG7_OFFSET) & 0xFFFF0000) | ((t) & 0xFFFF)) //!< Sets the PWM duty cycle threshold; threshold be greater than 1 and less than the PWM period. This threshold is ignored when the threshold ramp is enabled
199#define userio_set_pwm_ramp_en(baseaddr, d) Xil_Out32(baseaddr+W3_USERIO_SLV_REG9_OFFSET, ( (Xil_In32(baseaddr+W3_USERIO_SLV_REG9_OFFSET) & 0x7FFFFFFF) | ((d&0x1)<<31))) //!< Enables and disables the PWM threshold ramp logic. Ramp must be disabled when changing ramp min/max params
200#define userio_set_pwm_ramp_max(baseaddr, m) Xil_Out32(baseaddr+W3_USERIO_SLV_REG9_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG9_OFFSET) & 0xFFFF0000) | ((m) & 0xFFFF)) //!< Sets the max value of the ramped PWM threshold; must be greater than the ramp min value and less than the PWM period
201#define userio_set_pwm_ramp_min(baseaddr, m) Xil_Out32(baseaddr+W3_USERIO_SLV_REG9_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG9_OFFSET) & 0x8000FFFF) | (((m) & 0x7FFF)<<16)) //!< Sets the min value of the ramped PWM threshold; must be greater than 1 and less than the ramp max value
202
203//reg0 masks
204#define W3_USERIO_HEXDISP_L_MAPMODE     0x20000000 //!< Enables 4-bit to 7-segment mapping for left hex display
205#define W3_USERIO_HEXDISP_R_MAPMODE     0x10000000 //!< Enables 4-bit to 7-segment mapping for right hex display
206#define W3_USERIO_CTRLSRC_LED_RFB_RED   0x08000000 //!< Control source selection mask for red LED near RF B
207#define W3_USERIO_CTRLSRC_LED_RFB_GREEN 0x04000000 //!< Control source selection mask for green LED near RF B
208#define W3_USERIO_CTRLSRC_LED_RFA_RED   0x02000000 //!< Control source selection mask for red LED near RF A
209#define W3_USERIO_CTRLSRC_LED_RFA_GREEN 0x01000000 //!< Control source selection mask for green LED near RF A
210#define W3_USERIO_CTRLSRC_LEDS_RED      0x000F0000 //!< Control source selection mask for the red user LEDs
211#define W3_USERIO_CTRLSRC_LEDS_GREEN    0x00F00000 //!< Control source selection mask for the green user LEDs
212#define W3_USERIO_CTRLSRC_HEXDISP_R     0x0000FF00 //!< Control source selection mask for the left hex display (includes decimal point)
213#define W3_USERIO_CTRLSRC_HEXDISP_L     0x000000FF //!< Control source selection mask for the right hex display (includes decimal point)
214#define W3_USERIO_CTRLSRC_HEXDISP_DP_R  0x00008000 //!< Control source selection mask for the left hex display decimal point
215#define W3_USERIO_CTRLSRC_HEXDISP_DP_L  0x00000080 //!< Control source selection mask for the right hex display decimal point
216
217#define W3_USERIO_CTRLSRC_LEDS_RFA      (W3_USERIO_CTRLSRC_LED_RFA_RED | W3_USERIO_CTRLSRC_LED_RFA_GREEN) //!< Control source selection masks for both LEDs near RF A
218#define W3_USERIO_CTRLSRC_LEDS_RFB      (W3_USERIO_CTRLSRC_LED_RFB_RED | W3_USERIO_CTRLSRC_LED_RFB_GREEN) //!< Control source selection masks for both LEDs near RF B
219#define W3_USERIO_CTRLSRC_LEDS_RF       (W3_USERIO_CTRLSRC_LEDS_RFA | W3_USERIO_CTRLSRC_LEDS_RFB) //!< Control source selection masks for all RF LEDs
220#define W3_USERIO_CTRLSRC_LEDS          (W3_USERIO_CTRLSRC_LEDS_RED | W3_USERIO_CTRLSRC_LEDS_GREEN) //!< Control source selection masks for all user LEDs
221#define W3_USERIO_CTRLSRC_HEXDISPS      (W3_USERIO_CTRLSRC_HEXDISP_L | W3_USERIO_CTRLSRC_HEXDISP_R) //!< Control source selection masks for both hex displays
222
223#define W3_USERIO_CTRLSRC_ALL_OUTPUTS   (W3_USERIO_CTRLSRC_LEDS_RF | W3_USERIO_CTRLSRC_LEDS  | W3_USERIO_CTRLSRC_HEXDISPS) //!< Control source selection masks for all outputs
224/** @}*/
225
226
227/** \defgroup userio_read Reading user IO
228<b>Note on output state</b>: The macros for reading the current state of user outputs (LEDs, hex displays) can only access outputs configured for software control. Attempts to read the state
229of outputs configured for hardware control (i.e. outputs with corresponding CTRLSRC_* asserted in control reg) will not reflect actual output state.
230
231Examples:
232\code{.c}
233//Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h
234
235//Check if middle push button is being pressed
236if(userio_read_inputs(USERIO_BASEADDR) & W3_USERIO_PB_M) {...}
237
238//Read 4-bit DIP switch value
239u8 x = userio_read_inputs(USERIO_BASEADDR) & W3_USERIO_DIPSW;
240\endcode
241
242 *  \addtogroup userio_read
243 * @{
244 */
245#define userio_read_inputs(baseaddr)        Xil_In32(baseaddr+W3_USERIO_SLV_REG6_OFFSET) //!< Returns the current state of the user inputs (buttons and DIP switch)
246#define userio_read_hexdisp_left(baseaddr)  Xil_In32(baseaddr+W3_USERIO_SLV_REG1_OFFSET) //!< Returns the current state of the left hex display outputs
247#define userio_read_hexdisp_right(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG2_OFFSET) //!< Returns the current state of the right hex display outputs
248#define userio_read_leds_red(baseaddr)      Xil_In32(baseaddr+W3_USERIO_SLV_REG3_OFFSET) //!< Returns the current state of the red user LEDs
249#define userio_read_leds_green(baseaddr)    Xil_In32(baseaddr+W3_USERIO_SLV_REG4_OFFSET) //!< Returns the current state of the green user LEDs
250#define userio_read_leds_rf(baseaddr)       Xil_In32(baseaddr+W3_USERIO_SLV_REG5_OFFSET) //!< Returns the current state of the RF LEDs
251/** @}*/
252
253/** \defgroup userio_write Setting user outputs
254
255<b>Hex display notes:</b>
256The w3_userio core implements logic to map 4-bit values to the 7-segment representation of the corresponding hex value. When this mode
257is enabled via the control register (W3_USERIO_HEXDISP_x_MAPMODE is asserte), user code should write 4-bit values via the hex display macros below. When map
258mode is disabled, the user value is driven directly to the 7-segments of the hex display.
259
260The decimal point on each hex dipslay is controlled by OR'ing 4 bit (in map mode) or 7 bit (in non-map mode) value with W3_USERIO_HEXDISP_DP.
261
262Examples:
263\code{.c}
264//Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h
265
266//Display "B" on the left hex dipslay (assumes map mode is enabled; see control register docs)
267userio_write_hexdisp_left(USERIO_ADDR, 0xB);
268
269//Display "4" on the right hex dipslay and light the decimal point (assumes map mode is enabled; see control register docs)
270userio_write_hexdisp_right(USERIO_ADDR, (0x4 | W3_USERIO_HEXDISP_DP) );
271
272//Turn off all four green user LEDs
273userio_write_leds_green(USERIO_ADDR, 0);
274
275//Toggle the 2 LSB of the red user LEDs
276userio_toggle_leds_red(USERIO_ADDR, 0x3);
277
278\endcode
279 *  \addtogroup userio_write
280 * @{
281 */
282#define userio_write_hexdisp_left(baseaddr, x)  Xil_Out32(baseaddr+W3_USERIO_SLV_REG1_OFFSET, x) //!< Sets the left hex dispaly
283#define userio_write_hexdisp_right(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG2_OFFSET, x) //!< Sets the right hex dispaly
284#define userio_write_leds_red(baseaddr, x)      Xil_Out32(baseaddr+W3_USERIO_SLV_REG3_OFFSET, x) //!< Sets the 4 red LEDs when configured for software control (software control is default)
285#define userio_write_leds_green(baseaddr, x)    Xil_Out32(baseaddr+W3_USERIO_SLV_REG4_OFFSET, x) //!< Sets the 4 green LEDs when configured for software control (software control is default)
286#define userio_write_leds_rf(baseaddr, x)       Xil_Out32(baseaddr+W3_USERIO_SLV_REG5_OFFSET, x) //!< Sets the 4 RF LEDs when configured for software control (hardware control is default)
287#define userio_toggle_hexdisp_left(baseaddr, mask)  Xil_Out32(baseaddr+W3_USERIO_SLV_REG1_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG1_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask on left hex display
288#define userio_toggle_hexdisp_right(baseaddr, mask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG2_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG2_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask on right hex display
289#define userio_toggle_leds_red(baseaddr, mask)      Xil_Out32(baseaddr+W3_USERIO_SLV_REG3_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG3_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask in red LEDs
290#define userio_toggle_leds_green(baseaddr, mask)    Xil_Out32(baseaddr+W3_USERIO_SLV_REG4_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG4_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask in green LEDs
291#define userio_toggle_leds_rf(baseaddr, mask)       Xil_Out32(baseaddr+W3_USERIO_SLV_REG5_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG5_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask in RF LEDs
292/** @}*/
293
294/** \defgroup userio_masks Masks for user IO elements
295 *  \addtogroup userio_masks
296 * @{
297 */
298
299//reg1/reg2 masks
300#define W3_USERIO_HEXDISP_DP            0x100 //!< Mask for decimal point LEDs on hex displays
301
302//reg5 masks
303#define W3_USERIO_RFA_LED_GREEN         0x1 //!< Mask for green LED near RF A
304#define W3_USERIO_RFA_LED_RED           0x2 //!< Mask for red LED near RF A
305#define W3_USERIO_RFB_LED_GREEN         0x4 //!< Mask for green LED near RF B
306#define W3_USERIO_RFB_LED_RED           0x8 //!< Mask for red LED near RF B
307
308//reg6 masks
309#define W3_USERIO_PB_U  0x40 //!< Mask for up push button
310#define W3_USERIO_PB_M  0x20 //!< Mask for middle push button
311#define W3_USERIO_PB_D  0x10 //!< Mask for down push button
312#define W3_USERIO_DIPSW 0x0F //!< Mask for 4 positions of DIP switch
313/** @}*/
314
315/** \defgroup dbg_hdr Debug Header I/O
316The userio core implements an array of bi-directional buffers that can be routed to the WARP v3 board's debug header. The direction of each
317pin is configured at run time. This is similar to the Xilinx axi_gpio core. However the w3_userio implmenetaiton supports reading the current
318value of both inputs (like axi_gpi) and outputs (unlike axi_gpio). This allows read-modify-write of output bits, permitting simultaneous use
319of the debug header pins from multiple CPUs.
320
321 *  \addtogroup dbg_hdr
322 * @{
323 */
324//reg13 masks
325#define W3_USERIO_DBG_HDR_DIR_MASK      0xFFFF0000 //!< Mask for IOB direction control bits (1 per pin)
326#define W3_USERIO_DBG_HDR_VAL_MASK      0x0000FFFF //!< Mask for IOB data value bits (1 per pin)
327
328#define DBG_HDR_DIR_OUTPUT              0x0 //!< Value for dir argument to userio_set_dbg_hdr_io_dir() to set IOB as Output
329#define DBG_HDR_DIR_INPUT               0x1 //!< Value for dir argument to userio_set_dbg_hdr_io_dir() to set IOB as Input
330
331#define userio_set_dbg_hdr_io_dir(baseaddr, dir, pin_mask) Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \
332    (dir) ? \
333    (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) |  (((pin_mask) << 16) & W3_USERIO_DBG_HDR_DIR_MASK)) : \
334    (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) & ~(((pin_mask) << 16) & W3_USERIO_DBG_HDR_DIR_MASK))) //!< Sets direction (DBG_HDR_DIR_OUTPUT or DBG_HDR_DIR_INPUT) of pins specified in pin_mask
335
336#define userio_set_dbg_hdr_out(baseaddr, pin_mask) Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \
337    (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) | ((pin_mask) & W3_USERIO_DBG_HDR_VAL_MASK))) //!< Asserts selected output pins
338
339#define userio_clear_dbg_hdr_out(baseaddr, pin_mask) Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \
340    (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) & ~((pin_mask) & W3_USERIO_DBG_HDR_VAL_MASK)))  //!< De-asserts selected output pins
341
342#define userio_write_dbg_hdr_out(baseaddr, val) Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \
343    ((Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) & ~W3_USERIO_DBG_HDR_VAL_MASK) | ((pin_mask) & W3_USERIO_DBG_HDR_VAL_MASK)))  //!< Writes all output pins
344   
345#define userio_read_dbg_hdr_io(baseaddr) (Xil_In32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET) & W3_USERIO_DBG_HDR_VAL_MASK)  //!< Reads state of all pins (inputs and outputs)
346 
347 /** @}*/
348
349 
350/** \defgroup dna_read Reading FPGA DNA
351Every Virtex-6 FPGA has a unique "DNA" value embedded in the device. The w3_userio core implements logic to read this value into software-accessible registers. The
352DNA value is 56 bits, so two 32-bit registers are used to store the full value.
353
354<b>Hardware requirements:</b>
355<ul>
356<li>A clock signal slower than 100MHz must be connected to the w3_userio core DNA_Port_Clk port
357<li>The w3_userio core parameter INCLUDE_DNA_READ_LOGIC must be enabled
358</ul>
359If both requirements aren't met the DNA register values are undefined.
360
361The FPGA DNA value is also stored in the WARP v3 board EEPROM. Refer to the user guide EEPROM page for details.
362 *  \addtogroup dna_read
363 * @{
364 */
365#define userio_read_fpga_dna_lsb(baseaddr)  Xil_In32(baseaddr+W3_USERIO_SLV_REG12_OFFSET) //!< Returns the 32 LSB of the FPGA DNA
366#define userio_read_fpga_dna_msb(baseaddr)  Xil_In32(baseaddr+W3_USERIO_SLV_REG12_OFFSET) //!< Returns the 24 MSB of the FPGA DNA
367/** @}*/
368
369#endif /** W3_USERIO_H */
370
Note: See TracBrowser for help on using the repository browser.