[1927] | 1 | /***************************************************************** |
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| 2 | * File: w3_userio.h |
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[5615] | 3 | * Copyright (c) 2016 Mango Communications, all rights reseved |
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[1927] | 4 | * Released under the WARP License |
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[5615] | 5 | * See http://warpproject.org/license for details |
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[1927] | 6 | *****************************************************************/ |
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| 7 | |
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| 8 | /*! \file w3_userio.h |
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| 9 | |
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| 10 | \mainpage |
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| 11 | This is the driver for the w3_userio core, which provides access to all the user IO resources on WARP v3 boards. These resources include |
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| 12 | user LEDs, RF LEDs, hex displays, push buttons and a DIP switch. |
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| 13 | |
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| 14 | This driver only implements macros for reading/writing registers in the w3_userio core hardware. Macros are also provided to read the Virtex-6 device DNA. |
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| 15 | |
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[5539] | 16 | @version 1.02.a |
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| 17 | @copyright (c) 2011-2016 Mango Communications, Inc. All rights reserved.<br> |
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[5615] | 18 | Released under the WARP open source license (see http://warpproject.org/license) |
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[1927] | 19 | |
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| 20 | */ |
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| 21 | /* Address map: |
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| 22 | HDL is coded [31:0], adopting Xilinx's convention for AXI IPIF cores |
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| 23 | All registers are 32-bits |
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| 24 | regX[31] maps to 0x80000000 in C driver |
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| 25 | regX[0] maps to 0x00000001 in C driver |
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| 26 | |
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| 27 | 0: Control RW |
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| 28 | [31:30] = Reserved |
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| 29 | [ 29] = Left hex data mode (0=user supplies bit-per-segment; 1=user supplies 4-bit hex) 0x20000000 |
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| 30 | [ 28] = Right hex data mode (0=user supplies bit-per-segment; 1=user supplies 4-bit hex) 0x10000000 |
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| 31 | Control source for LEDs: 0=software controlled, 1=usr_ port controlled |
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| 32 | [27:24] = {rfb_red rfb_green rfa_red rfa_green} 0x0F000000 |
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| 33 | [23:16] = {leds_red leds_green} 0x00FF0000 |
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[3463] | 34 | [15: 8] = {hexdisp_right{a b c d e f g dp}} 0x0000FF00 |
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| 35 | [ 7: 0] = {hexdisp_left{a b c d e f g dp}} 0x000000FF !! Left/Right are swapped in user_logic.v comments |
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[1927] | 36 | 1: Left hex display RW |
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| 37 | [31: 9] = reserved |
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| 38 | [ 8] = DP (controlled directly; doesn't depend on data mode) 0x100 |
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| 39 | [ 6: 0] = Data value ([6:4] ignored when data mode = 1) 0x03F |
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| 40 | 2: Right hex display RW |
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| 41 | [31: 9] = reserved |
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| 42 | [ 8] = DP (controlled directly; doesn't depend on data mode) 0x100 |
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| 43 | [ 6: 0] = Data value ([6:4] ignored when data mode = 1) 0x03F |
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| 44 | 3: Red user LEDs RW |
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| 45 | [31: 4] = reserved |
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| 46 | [ 3: 0] = Data value (1=LED illuminated) 0xF, with 0x1 mapped to lowest LED |
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| 47 | 4: Green user LEDs RW |
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| 48 | [31: 4] = reserved |
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| 49 | [ 3: 0] = Data value (1=LED illuminated) 0xF, with 0x1 mapped to lowest LED |
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| 50 | 5: RF LEDs RW |
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| 51 | [31: 4] = reserved |
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| 52 | [ 3] = rfb_red 0x8 |
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| 53 | [ 2] = rfb_green 0x4 |
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| 54 | [ 1] = rfa_red 0x2 |
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| 55 | [ 0] = rfa_green 0x1 |
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| 56 | 6: Switch/button inputs RO |
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| 57 | [31: 7] = reserved |
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| 58 | [ 6] = pb_up 0x40 |
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| 59 | [ 5] = pb_mid 0x20 |
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| 60 | [ 4] = pb_down 0x10 |
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| 61 | [ 3: 0] = DIP switch 0x0F (with 0x1 mapped to right-most switch) |
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| 62 | |
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[2825] | 63 | 7: PWM Gen Param: PWM period RW |
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| 64 | [31:29] = reserved |
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| 65 | [28: 0] = PWN period |
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[1927] | 66 | |
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[2825] | 67 | 8: PWM Gen Param: PWM output deassert thresh RW |
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| 68 | [31:29] = reserved |
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| 69 | [28: 0] = PWM output deassert thresh |
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| 70 | |
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| 71 | 9: PWM Gen Param: PWM ramp step RW |
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| 72 | [31] = ramp enabled |
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| 73 | [30:20] = reserved |
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| 74 | [19: 0] = PWM thresh ramp step |
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| 75 | |
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| 76 | 10: HW Output control sel RW |
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| 77 | [31:28] = Reserved |
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| 78 | HW Control source for LEDs: 0=usr_ ports, 1=pwm gen (same ctrlSrc masks as reg0) |
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| 79 | [27:24] = {rfb_red rfb_green rfa_red rfa_green} 0x0F000000 |
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| 80 | [23:16] = {leds_red leds_green} 0x00FF0000 |
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| 81 | [15: 8] = {hexdisp_left{a b c d e f g dp}} 0x0000FF00 |
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| 82 | [ 7: 0] = {hexdisp_right{a b c d e f g dp}} 0x000000FF |
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| 83 | |
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| 84 | 11: FPGA DNA LSB |
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| 85 | [31: 0] = 32LSB of FPGA DNA |
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| 86 | |
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| 87 | 12: FPGA DNA MSB |
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| 88 | [31:25] = reserved |
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| 89 | [24: 0] = FPGA DNA 25MSB |
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[5539] | 90 | |
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| 91 | 13: Debug Header IO |
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| 92 | [31:16] = IOB direction control, 1 bit per pin; only C_DBG_HDR_WIDTH LSB are used |
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| 93 | [15: 0] = IOB data. Bits corresponding to inputs contain input values. Bits |
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| 94 | corresponding to outputs contain output values. Bits corresponding to |
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| 95 | unused pins contain would-be output values (whatever software last wrote). |
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[2825] | 96 | */ |
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| 97 | |
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[1927] | 98 | #ifndef W3_USERIO_H |
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| 99 | #define W3_USERIO_H |
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| 100 | |
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| 101 | #include "xil_io.h" |
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| 102 | |
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| 103 | /// @cond EXCLUDE_FROM_DOCS |
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| 104 | // Address offset for each slave register; exclude from docs, as users never use these directly |
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| 105 | #define W3_USERIO_USER_SLV_SPACE_OFFSET (0x00000000) |
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| 106 | #define W3_USERIO_SLV_REG0_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000000) |
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| 107 | #define W3_USERIO_SLV_REG1_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000004) |
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| 108 | #define W3_USERIO_SLV_REG2_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000008) |
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| 109 | #define W3_USERIO_SLV_REG3_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x0000000C) |
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| 110 | #define W3_USERIO_SLV_REG4_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000010) |
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| 111 | #define W3_USERIO_SLV_REG5_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000014) |
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| 112 | #define W3_USERIO_SLV_REG6_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000018) |
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| 113 | #define W3_USERIO_SLV_REG7_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x0000001C) |
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| 114 | #define W3_USERIO_SLV_REG8_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000020) |
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| 115 | #define W3_USERIO_SLV_REG9_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000024) |
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| 116 | #define W3_USERIO_SLV_REG10_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000028) |
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| 117 | #define W3_USERIO_SLV_REG11_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x0000002C) |
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[2825] | 118 | #define W3_USERIO_SLV_REG12_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000030) |
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[5539] | 119 | #define W3_USERIO_SLV_REG13_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000034) |
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[1927] | 120 | /// @endcond |
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| 121 | |
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[2827] | 122 | /** \defgroup control_reg Control registers |
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[1927] | 123 | * \addtogroup control_reg |
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| 124 | <b>Hardware vs. software control</b>: |
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| 125 | Every LED and hex display segment can be controlled either via software or hardware: |
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| 126 | <ul> |
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[2827] | 127 | <li><b>Software</b>: user code sets LED state by writing a 1 to the corresponding register bit |
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| 128 | <li><b>Hardware</b>: Two modes:<ul> |
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| 129 | <li><b>Port mode</b>: LED state is controlled by corresponding usr_* port |
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| 130 | <li><b>PWM mode</b>: LED state is controlled by internal PWM waveform generator |
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| 131 | </ul> |
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[1927] | 132 | </ul> |
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| 133 | |
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[2826] | 134 | The WARP reference designs use hardware/port control for the RF LEDs (to indicate real-time Tx/Rx state of each RF interface) and software control |
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[1927] | 135 | for all other LED/hex display outputs. |
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| 136 | |
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| 137 | The control source (hw or sw) for each output bit is set by the control register described below. |
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| 138 | |
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| 139 | Examples: |
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| 140 | \code{.c} |
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| 141 | //Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h |
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| 142 | |
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[2827] | 143 | //------------------------------------------------------------------------------ |
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| 144 | // Set both hex dipslays to map 4-bit to 7-segment values automatically |
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[1927] | 145 | userio_write_control(USERIO_BASEADDR, (W3_USERIO_HEXDISP_L_MAPMODE | W3_USERIO_HEXDISP_R_MAPMODE)); |
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| 146 | |
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[2827] | 147 | //------------------------------------------------------------------------------ |
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| 148 | // Select software control of all outputs |
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[1927] | 149 | userio_set_ctrlSrc_sw(USERIO_BASEADDR, (W3_USERIO_CTRLSRC_LEDS_RF | W3_USERIO_CTRLSRC_LEDS | W3_USERIO_CTRLSRC_HEXDISPS)); |
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| 150 | |
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[2827] | 151 | //------------------------------------------------------------------------------ |
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| 152 | // Select hardware/port control of RF LEDs |
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[1927] | 153 | userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RF); |
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| 154 | |
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[2827] | 155 | //------------------------------------------------------------------------------ |
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| 156 | // Enable hardware control of green user LEDs, software control of red user LEDs |
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[1927] | 157 | userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_GREEN); |
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| 158 | userio_set_ctrlSrc_sw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED); |
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[2826] | 159 | |
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[2827] | 160 | //------------------------------------------------------------------------------ |
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| 161 | // Use the PWM generator to slowly blink the green LEDs |
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[2826] | 162 | userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_GREEN); |
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| 163 | userio_set_hw_ctrl_mode_pwm(USERIO_BASEADDR, (W3_USERIO_CTRLSRC_LEDS_GREEN); |
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| 164 | userio_set_pwm_ramp_en(USERIO_BASEADDR, 0); |
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| 165 | userio_set_pwm_period(USERIO_BASEADDR, 65530); |
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| 166 | userio_set_pwm_thresh(USERIO_BASEADDR, 65530/2); |
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| 167 | |
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[2827] | 168 | //------------------------------------------------------------------------------ |
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| 169 | // Use the PWM generator to show a "sleep" pattern on red LEDs |
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[2826] | 170 | userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED); |
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| 171 | userio_set_hw_ctrl_mode_pwm(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED); |
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| 172 | |
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[2827] | 173 | //Use fast period so blinking is not visable |
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| 174 | // (fast blink with low duty cycle looks like a dim constant brightness) |
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[2826] | 175 | userio_set_pwm_period(USERIO_BASEADDR, 500); |
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| 176 | |
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| 177 | //Ramp must be disabled when changing ramp params |
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| 178 | userio_set_pwm_ramp_en(USERIO_BASEADDR, 0); |
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| 179 | userio_set_pwm_ramp_min(USERIO_BASEADDR, 2); |
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| 180 | userio_set_pwm_ramp_max(USERIO_BASEADDR, 250); |
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| 181 | userio_set_pwm_ramp_en(USERIO_BASEADDR, 1); |
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[1927] | 182 | \endcode |
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| 183 | |
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| 184 | * @{ |
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| 185 | */ |
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| 186 | |
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| 187 | #define userio_read_control(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) //!< Returns the value of the control register |
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| 188 | #define userio_write_control(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, x) //!< Sets the control register to x |
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| 189 | |
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[2826] | 190 | #define userio_set_ctrlSrc_sw(baseaddr, ioMask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) & ~(ioMask)))//!< Sets selected outputs to software control (register writes) |
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[1927] | 191 | #define userio_set_ctrlSrc_hw(baseaddr, ioMask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) | (ioMask))) //!< Sets selected outputs to hardware control (usr_ ports) |
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| 192 | |
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[2826] | 193 | #define userio_set_hw_ctrl_mode_pwm(baseaddr, ioMask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG10_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG10_OFFSET) | (ioMask))) //!< Sets selected outputs to use PWM generator for hardware/PWM control |
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| 194 | #define userio_set_hw_ctrl_mode_port(baseaddr, ioMask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG10_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG10_OFFSET) & (~ioMask))) //!< Sets selected outputs to use PWM generator for hardware/port control |
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[2825] | 195 | |
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| 196 | //PWM config macros |
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[2826] | 197 | #define userio_set_pwm_period(baseaddr, p) Xil_Out32(baseaddr+W3_USERIO_SLV_REG7_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG7_OFFSET) & 0x0000FFFF) | (((p) & 0xFFFF)<<16)) //!< Sets the PWM period; larger periods result in slower blinking |
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| 198 | #define userio_set_pwm_thresh(baseaddr, t) Xil_Out32(baseaddr+W3_USERIO_SLV_REG7_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG7_OFFSET) & 0xFFFF0000) | ((t) & 0xFFFF)) //!< Sets the PWM duty cycle threshold; threshold be greater than 1 and less than the PWM period. This threshold is ignored when the threshold ramp is enabled |
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| 199 | #define userio_set_pwm_ramp_en(baseaddr, d) Xil_Out32(baseaddr+W3_USERIO_SLV_REG9_OFFSET, ( (Xil_In32(baseaddr+W3_USERIO_SLV_REG9_OFFSET) & 0x7FFFFFFF) | ((d&0x1)<<31))) //!< Enables and disables the PWM threshold ramp logic. Ramp must be disabled when changing ramp min/max params |
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| 200 | #define userio_set_pwm_ramp_max(baseaddr, m) Xil_Out32(baseaddr+W3_USERIO_SLV_REG9_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG9_OFFSET) & 0xFFFF0000) | ((m) & 0xFFFF)) //!< Sets the max value of the ramped PWM threshold; must be greater than the ramp min value and less than the PWM period |
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| 201 | #define userio_set_pwm_ramp_min(baseaddr, m) Xil_Out32(baseaddr+W3_USERIO_SLV_REG9_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG9_OFFSET) & 0x8000FFFF) | (((m) & 0x7FFF)<<16)) //!< Sets the min value of the ramped PWM threshold; must be greater than 1 and less than the ramp max value |
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[2825] | 202 | |
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[1927] | 203 | //reg0 masks |
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| 204 | #define W3_USERIO_HEXDISP_L_MAPMODE 0x20000000 //!< Enables 4-bit to 7-segment mapping for left hex display |
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| 205 | #define W3_USERIO_HEXDISP_R_MAPMODE 0x10000000 //!< Enables 4-bit to 7-segment mapping for right hex display |
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| 206 | #define W3_USERIO_CTRLSRC_LED_RFB_RED 0x08000000 //!< Control source selection mask for red LED near RF B |
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| 207 | #define W3_USERIO_CTRLSRC_LED_RFB_GREEN 0x04000000 //!< Control source selection mask for green LED near RF B |
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| 208 | #define W3_USERIO_CTRLSRC_LED_RFA_RED 0x02000000 //!< Control source selection mask for red LED near RF A |
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| 209 | #define W3_USERIO_CTRLSRC_LED_RFA_GREEN 0x01000000 //!< Control source selection mask for green LED near RF A |
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| 210 | #define W3_USERIO_CTRLSRC_LEDS_RED 0x000F0000 //!< Control source selection mask for the red user LEDs |
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| 211 | #define W3_USERIO_CTRLSRC_LEDS_GREEN 0x00F00000 //!< Control source selection mask for the green user LEDs |
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[3462] | 212 | #define W3_USERIO_CTRLSRC_HEXDISP_R 0x0000FF00 //!< Control source selection mask for the left hex display (includes decimal point) |
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| 213 | #define W3_USERIO_CTRLSRC_HEXDISP_L 0x000000FF //!< Control source selection mask for the right hex display (includes decimal point) |
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| 214 | #define W3_USERIO_CTRLSRC_HEXDISP_DP_R 0x00008000 //!< Control source selection mask for the left hex display decimal point |
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| 215 | #define W3_USERIO_CTRLSRC_HEXDISP_DP_L 0x00000080 //!< Control source selection mask for the right hex display decimal point |
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[1927] | 216 | |
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| 217 | #define W3_USERIO_CTRLSRC_LEDS_RFA (W3_USERIO_CTRLSRC_LED_RFA_RED | W3_USERIO_CTRLSRC_LED_RFA_GREEN) //!< Control source selection masks for both LEDs near RF A |
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| 218 | #define W3_USERIO_CTRLSRC_LEDS_RFB (W3_USERIO_CTRLSRC_LED_RFB_RED | W3_USERIO_CTRLSRC_LED_RFB_GREEN) //!< Control source selection masks for both LEDs near RF B |
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| 219 | #define W3_USERIO_CTRLSRC_LEDS_RF (W3_USERIO_CTRLSRC_LEDS_RFA | W3_USERIO_CTRLSRC_LEDS_RFB) //!< Control source selection masks for all RF LEDs |
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| 220 | #define W3_USERIO_CTRLSRC_LEDS (W3_USERIO_CTRLSRC_LEDS_RED | W3_USERIO_CTRLSRC_LEDS_GREEN) //!< Control source selection masks for all user LEDs |
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| 221 | #define W3_USERIO_CTRLSRC_HEXDISPS (W3_USERIO_CTRLSRC_HEXDISP_L | W3_USERIO_CTRLSRC_HEXDISP_R) //!< Control source selection masks for both hex displays |
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[2825] | 222 | |
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[2826] | 223 | #define W3_USERIO_CTRLSRC_ALL_OUTPUTS (W3_USERIO_CTRLSRC_LEDS_RF | W3_USERIO_CTRLSRC_LEDS | W3_USERIO_CTRLSRC_HEXDISPS) //!< Control source selection masks for all outputs |
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[1927] | 224 | /** @}*/ |
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| 225 | |
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| 226 | |
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| 227 | /** \defgroup userio_read Reading user IO |
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| 228 | <b>Note on output state</b>: The macros for reading the current state of user outputs (LEDs, hex displays) can only access outputs configured for software control. Attempts to read the state |
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| 229 | of outputs configured for hardware control (i.e. outputs with corresponding CTRLSRC_* asserted in control reg) will not reflect actual output state. |
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| 230 | |
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| 231 | Examples: |
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| 232 | \code{.c} |
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| 233 | //Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h |
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| 234 | |
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| 235 | //Check if middle push button is being pressed |
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| 236 | if(userio_read_inputs(USERIO_BASEADDR) & W3_USERIO_PB_M) {...} |
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| 237 | |
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| 238 | //Read 4-bit DIP switch value |
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| 239 | u8 x = userio_read_inputs(USERIO_BASEADDR) & W3_USERIO_DIPSW; |
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| 240 | \endcode |
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| 241 | |
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| 242 | * \addtogroup userio_read |
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| 243 | * @{ |
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| 244 | */ |
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| 245 | #define userio_read_inputs(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG6_OFFSET) //!< Returns the current state of the user inputs (buttons and DIP switch) |
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| 246 | #define userio_read_hexdisp_left(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG1_OFFSET) //!< Returns the current state of the left hex display outputs |
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| 247 | #define userio_read_hexdisp_right(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG2_OFFSET) //!< Returns the current state of the right hex display outputs |
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| 248 | #define userio_read_leds_red(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG3_OFFSET) //!< Returns the current state of the red user LEDs |
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| 249 | #define userio_read_leds_green(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG4_OFFSET) //!< Returns the current state of the green user LEDs |
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| 250 | #define userio_read_leds_rf(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG5_OFFSET) //!< Returns the current state of the RF LEDs |
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| 251 | /** @}*/ |
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| 252 | |
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| 253 | /** \defgroup userio_write Setting user outputs |
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| 254 | |
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| 255 | <b>Hex display notes:</b> |
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| 256 | The w3_userio core implements logic to map 4-bit values to the 7-segment representation of the corresponding hex value. When this mode |
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| 257 | is enabled via the control register (W3_USERIO_HEXDISP_x_MAPMODE is asserte), user code should write 4-bit values via the hex display macros below. When map |
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| 258 | mode is disabled, the user value is driven directly to the 7-segments of the hex display. |
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| 259 | |
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| 260 | The decimal point on each hex dipslay is controlled by OR'ing 4 bit (in map mode) or 7 bit (in non-map mode) value with W3_USERIO_HEXDISP_DP. |
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| 261 | |
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| 262 | Examples: |
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| 263 | \code{.c} |
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| 264 | //Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h |
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| 265 | |
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| 266 | //Display "B" on the left hex dipslay (assumes map mode is enabled; see control register docs) |
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| 267 | userio_write_hexdisp_left(USERIO_ADDR, 0xB); |
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| 268 | |
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| 269 | //Display "4" on the right hex dipslay and light the decimal point (assumes map mode is enabled; see control register docs) |
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| 270 | userio_write_hexdisp_right(USERIO_ADDR, (0x4 | W3_USERIO_HEXDISP_DP) ); |
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| 271 | |
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| 272 | //Turn off all four green user LEDs |
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| 273 | userio_write_leds_green(USERIO_ADDR, 0); |
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| 274 | |
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| 275 | //Toggle the 2 LSB of the red user LEDs |
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| 276 | userio_toggle_leds_red(USERIO_ADDR, 0x3); |
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| 277 | |
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| 278 | \endcode |
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| 279 | * \addtogroup userio_write |
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| 280 | * @{ |
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| 281 | */ |
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| 282 | #define userio_write_hexdisp_left(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG1_OFFSET, x) //!< Sets the left hex dispaly |
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| 283 | #define userio_write_hexdisp_right(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG2_OFFSET, x) //!< Sets the right hex dispaly |
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| 284 | #define userio_write_leds_red(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG3_OFFSET, x) //!< Sets the 4 red LEDs when configured for software control (software control is default) |
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| 285 | #define userio_write_leds_green(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG4_OFFSET, x) //!< Sets the 4 green LEDs when configured for software control (software control is default) |
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| 286 | #define userio_write_leds_rf(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG5_OFFSET, x) //!< Sets the 4 RF LEDs when configured for software control (hardware control is default) |
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| 287 | #define userio_toggle_hexdisp_left(baseaddr, mask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG1_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG1_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask on left hex display |
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| 288 | #define userio_toggle_hexdisp_right(baseaddr, mask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG2_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG2_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask on right hex display |
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| 289 | #define userio_toggle_leds_red(baseaddr, mask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG3_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG3_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask in red LEDs |
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| 290 | #define userio_toggle_leds_green(baseaddr, mask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG4_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG4_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask in green LEDs |
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| 291 | #define userio_toggle_leds_rf(baseaddr, mask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG5_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG5_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask in RF LEDs |
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| 292 | /** @}*/ |
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| 293 | |
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| 294 | /** \defgroup userio_masks Masks for user IO elements |
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| 295 | * \addtogroup userio_masks |
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| 296 | * @{ |
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| 297 | */ |
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| 298 | |
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| 299 | //reg1/reg2 masks |
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| 300 | #define W3_USERIO_HEXDISP_DP 0x100 //!< Mask for decimal point LEDs on hex displays |
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| 301 | |
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| 302 | //reg5 masks |
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| 303 | #define W3_USERIO_RFA_LED_GREEN 0x1 //!< Mask for green LED near RF A |
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| 304 | #define W3_USERIO_RFA_LED_RED 0x2 //!< Mask for red LED near RF A |
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| 305 | #define W3_USERIO_RFB_LED_GREEN 0x4 //!< Mask for green LED near RF B |
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| 306 | #define W3_USERIO_RFB_LED_RED 0x8 //!< Mask for red LED near RF B |
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| 307 | |
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| 308 | //reg6 masks |
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| 309 | #define W3_USERIO_PB_U 0x40 //!< Mask for up push button |
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| 310 | #define W3_USERIO_PB_M 0x20 //!< Mask for middle push button |
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| 311 | #define W3_USERIO_PB_D 0x10 //!< Mask for down push button |
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| 312 | #define W3_USERIO_DIPSW 0x0F //!< Mask for 4 positions of DIP switch |
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| 313 | /** @}*/ |
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| 314 | |
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[5539] | 315 | /** \defgroup dbg_hdr Debug Header I/O |
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| 316 | The userio core implements an array of bi-directional buffers that can be routed to the WARP v3 board's debug header. The direction of each |
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| 317 | pin is configured at run time. This is similar to the Xilinx axi_gpio core. However the w3_userio implmenetaiton supports reading the current |
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| 318 | value of both inputs (like axi_gpi) and outputs (unlike axi_gpio). This allows read-modify-write of output bits, permitting simultaneous use |
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| 319 | of the debug header pins from multiple CPUs. |
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| 320 | |
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| 321 | * \addtogroup dbg_hdr |
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| 322 | * @{ |
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| 323 | */ |
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| 324 | //reg13 masks |
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| 325 | #define W3_USERIO_DBG_HDR_DIR_MASK 0xFFFF0000 //!< Mask for IOB direction control bits (1 per pin) |
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| 326 | #define W3_USERIO_DBG_HDR_VAL_MASK 0x0000FFFF //!< Mask for IOB data value bits (1 per pin) |
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| 327 | |
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[5615] | 328 | #define DBG_HDR_DIR_OUTPUT 0x0 //!< Value for dir argument to userio_set_dbg_hdr_io_dir() to set IOB as Output |
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| 329 | #define DBG_HDR_DIR_INPUT 0x1 //!< Value for dir argument to userio_set_dbg_hdr_io_dir() to set IOB as Input |
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[5539] | 330 | |
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| 331 | #define userio_set_dbg_hdr_io_dir(baseaddr, dir, pin_mask) Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \ |
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| 332 | (dir) ? \ |
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| 333 | (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) | (((pin_mask) << 16) & W3_USERIO_DBG_HDR_DIR_MASK)) : \ |
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[5615] | 334 | (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) & ~(((pin_mask) << 16) & W3_USERIO_DBG_HDR_DIR_MASK))) //!< Sets direction (DBG_HDR_DIR_OUTPUT or DBG_HDR_DIR_INPUT) of pins specified in pin_mask |
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[5539] | 335 | |
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| 336 | #define userio_set_dbg_hdr_out(baseaddr, pin_mask) Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \ |
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[5615] | 337 | (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) | ((pin_mask) & W3_USERIO_DBG_HDR_VAL_MASK))) //!< Asserts selected output pins |
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[5539] | 338 | |
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| 339 | #define userio_clear_dbg_hdr_out(baseaddr, pin_mask) Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \ |
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[5615] | 340 | (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) & ~((pin_mask) & W3_USERIO_DBG_HDR_VAL_MASK))) //!< De-asserts selected output pins |
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[5539] | 341 | |
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| 342 | #define userio_write_dbg_hdr_out(baseaddr, val) Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \ |
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[5615] | 343 | ((Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) & ~W3_USERIO_DBG_HDR_VAL_MASK) | ((pin_mask) & W3_USERIO_DBG_HDR_VAL_MASK))) //!< Writes all output pins |
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[5539] | 344 | |
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[5615] | 345 | #define userio_read_dbg_hdr_io(baseaddr) (Xil_In32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET) & W3_USERIO_DBG_HDR_VAL_MASK) //!< Reads state of all pins (inputs and outputs) |
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[5539] | 346 | |
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| 347 | /** @}*/ |
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| 348 | |
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| 349 | |
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[1927] | 350 | /** \defgroup dna_read Reading FPGA DNA |
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| 351 | Every Virtex-6 FPGA has a unique "DNA" value embedded in the device. The w3_userio core implements logic to read this value into software-accessible registers. The |
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| 352 | DNA value is 56 bits, so two 32-bit registers are used to store the full value. |
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| 353 | |
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| 354 | <b>Hardware requirements:</b> |
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| 355 | <ul> |
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| 356 | <li>A clock signal slower than 100MHz must be connected to the w3_userio core DNA_Port_Clk port |
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| 357 | <li>The w3_userio core parameter INCLUDE_DNA_READ_LOGIC must be enabled |
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| 358 | </ul> |
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| 359 | If both requirements aren't met the DNA register values are undefined. |
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| 360 | |
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| 361 | The FPGA DNA value is also stored in the WARP v3 board EEPROM. Refer to the user guide EEPROM page for details. |
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| 362 | * \addtogroup dna_read |
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| 363 | * @{ |
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| 364 | */ |
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[2825] | 365 | #define userio_read_fpga_dna_lsb(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG12_OFFSET) //!< Returns the 32 LSB of the FPGA DNA |
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| 366 | #define userio_read_fpga_dna_msb(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG12_OFFSET) //!< Returns the 24 MSB of the FPGA DNA |
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[1927] | 367 | /** @}*/ |
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| 368 | |
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| 369 | #endif /** W3_USERIO_H */ |
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| 370 | |
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