1 | ###################################################################
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2 | ##
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3 | ## Name : w3_userio
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4 | ## Desc : Microprocessor Peripheral Description
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5 | ## : Automatically generated by PsfUtility
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6 | ##
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7 | ###################################################################
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8 |
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9 | BEGIN w3_userio
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10 |
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11 | ## Peripheral Options
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12 | OPTION IPTYPE = PERIPHERAL
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13 | OPTION IMP_NETLIST = TRUE
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14 | OPTION HDL = MIXED
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15 | OPTION IP_GROUP = MICROBLAZE:PPC:USER
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16 | OPTION DESC = W3_USERIO
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17 | OPTION USAGE_LEVEL = BASE_USER
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18 | OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
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19 | OPTION DESC = WARP v3 User I/O
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20 | OPTION LONG_DESC = "Manages interface to all user IO on WARP v3 board. LED outputs can be controlled by software-accessible registers or ports. The control source for each LED is configured independently via a control register. DIP switch and buttons are debounced and captured in a register and driven to output ports."
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21 | OPTION IP_GROUP = USER
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22 |
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23 | IO_INTERFACE IO_IF = ext_userio, IO_TYPE = W3_USERIO_V1
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24 | IO_INTERFACE IO_IF = user_ports, IO_TYPE = W3_USERIO_V1
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25 |
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26 | ## Bus Interfaces
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27 | BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
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28 |
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29 | ## Generics for VHDL or Parameters for Verilog
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30 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
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31 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
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32 | PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
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33 | PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
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34 | PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
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35 | PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
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36 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
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37 | PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
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38 | PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
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39 | PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
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40 | PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
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41 | PARAMETER C_INCLUDE_DPHASE_TIMER = 0, DT = INTEGER, RANGE = (0, 1)
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42 | PARAMETER C_FAMILY = virtex6, DT = STRING
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43 |
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44 | PARAMETER HEXDISP_ACTIVE_HIGH = 0, DT = INTEGER, RANGE = (0, 1), VALUES = (0=Active Low, 1=Active High), DESC = "Selects whether hex displays are active high or low on WARP v3 board.", PERMIT = BASE_USER
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45 | PARAMETER INCLUDE_DNA_READ_LOGIC = 1, DT = INTEGER, RANGE = (0, 1), VALUES = (0=Do not include DNA read logic, 1=Include DNA read logic), Desc = "Selects whether to include logic to read the Virtex-6 device DNA value. If you use the DNA_PORT primitive elsewhere in the design, it should be excluded here.", PERMIT = BASE_USER
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46 |
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47 | ## Ports
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48 | PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
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49 | PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
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50 | PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
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51 | PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
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52 | PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
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53 | PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
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54 | PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
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55 | PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
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56 | PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
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57 | PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
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58 | PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
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59 | PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
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60 | PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
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61 | PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
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62 | PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
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63 | PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
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64 | PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
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65 | PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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66 | PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
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67 | PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
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68 | PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
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69 | PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
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70 | PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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71 | PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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72 | PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
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73 | PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
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74 | PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
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75 | PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
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76 | PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
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77 | PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
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78 | PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
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79 | PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
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80 | PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
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81 | PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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82 | PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
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83 | PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
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84 | PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
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85 | PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
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86 | PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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87 | PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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88 | PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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89 | PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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90 |
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91 | PORT hexdisp_left = "", DIR = O, VEC = [0:6], IO_IS = hexdisp_left, IO_IF = ext_userio
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92 | PORT hexdisp_right = "", DIR = O, VEC = [0:6], IO_IS = hexdisp_right, IO_IF = ext_userio
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93 | PORT hexdisp_left_dp = "", DIR = O, IO_IS = hexdisp_left_dp, IO_IF = ext_userio
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94 | PORT hexdisp_right_dp = "", DIR = O, IO_IS = hexdisp_right_dp, IO_IF = ext_userio
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95 |
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96 | PORT leds_red = "", DIR = O, VEC = [0:3], IO_IS = leds_red, IO_IF = ext_userio
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97 | PORT leds_green = "", DIR = O, VEC = [0:3], IO_IS = leds_green, IO_IF = ext_userio
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98 |
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99 | PORT rfa_led_red = "", DIR = O, IO_IS = rfa_led_red, IO_IF = ext_userio
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100 | PORT rfa_led_green = "", DIR = O, IO_IS = rfa_led_green, IO_IF = ext_userio
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101 | PORT rfb_led_red = "", DIR = O, IO_IS = rfb_led_red, IO_IF = ext_userio
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102 | PORT rfb_led_green = "", DIR = O, IO_IS = rfb_led_green, IO_IF = ext_userio
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103 |
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104 | PORT dipsw = "", DIR = I, VEC = [0:3], IO_IS = dipsw, IO_IF = ext_userio
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105 | PORT pb_u = "", DIR = I, IO_IS = pb_u, IO_IF = ext_userio
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106 | PORT pb_m = "", DIR = I, IO_IS = pb_m, IO_IF = ext_userio
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107 | PORT pb_d = "", DIR = I, IO_IS = pb_d, IO_IF = ext_userio
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108 |
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109 | PORT usr_hexdisp_left = "", DIR = I, VEC = [0:6], IO_IS = usr_hexdisp_left, IO_IF = user_ports
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110 | PORT usr_hexdisp_right = "", DIR = I, VEC = [0:6], IO_IS = usr_hexdisp_right, IO_IF = user_ports
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111 | PORT usr_hexdisp_left_dp = "", DIR = I, IO_IS = usr_hexdisp_left_dp, IO_IF = user_ports
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112 | PORT usr_hexdisp_right_dp = "", DIR = I, IO_IS = usr_hexdisp_right_dp, IO_IF = user_ports
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113 |
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114 | PORT usr_leds_red = "", DIR = I, VEC = [0:3], IO_IS = usr_leds_red, IO_IF = user_ports
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115 | PORT usr_leds_green = "", DIR = I, VEC = [0:3], IO_IS = usr_leds_green, IO_IF = user_ports
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116 |
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117 | PORT usr_rfa_led_red = "", DIR = I, IO_IS = usr_rfa_led_red, IO_IF = user_ports
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118 | PORT usr_rfa_led_green = "", DIR = I, IO_IS = usr_rfa_led_green, IO_IF = user_ports
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119 | PORT usr_rfb_led_red = "", DIR = I, IO_IS = usr_rfb_led_red, IO_IF = user_ports
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120 | PORT usr_rfb_led_green = "", DIR = I, IO_IS = usr_rfb_led_green, IO_IF = user_ports
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121 |
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122 | PORT usr_dipsw = "", DIR = O, VEC = [0:3], IO_IS = usr_dipsw, IO_IF = user_ports
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123 | PORT usr_pb_u = "", DIR = O, IO_IS = usr_pb_u, IO_IF = user_ports
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124 | PORT usr_pb_m = "", DIR = O, IO_IS = usr_pb_m, IO_IF = user_ports
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125 | PORT usr_pb_d = "", DIR = O, IO_IS = usr_pb_d, IO_IF = user_ports
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126 |
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127 | PORT DNA_Port_Clk = "", DIR = I, SIGIS = CLK, CLK_FREQ = 25000000
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128 | END
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