1 | |
---|
2 | //----------------------------------------------------------------- |
---|
3 | // System Generator version 10.1.3 VERILOG source file. |
---|
4 | // |
---|
5 | // Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
6 | // text/file contains proprietary, confidential information of Xilinx, |
---|
7 | // Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
8 | // copied and/or disclosed only pursuant to the terms of a valid license |
---|
9 | // agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
10 | // this text/file solely for design, simulation, implementation and |
---|
11 | // creation of design files limited to Xilinx devices or technologies. |
---|
12 | // Use with non-Xilinx devices or technologies is expressly prohibited |
---|
13 | // and immediately terminates your license unless covered by a separate |
---|
14 | // agreement. |
---|
15 | // |
---|
16 | // Xilinx is providing this design, code, or information "as is" solely |
---|
17 | // for use in developing programs and solutions for Xilinx devices. By |
---|
18 | // providing this design, code, or information as one possible |
---|
19 | // implementation of this feature, application or standard, Xilinx is |
---|
20 | // making no representation that this implementation is free from any |
---|
21 | // claims of infringement. You are responsible for obtaining any rights |
---|
22 | // you may require for your implementation. Xilinx expressly disclaims |
---|
23 | // any warranty whatsoever with respect to the adequacy of the |
---|
24 | // implementation, including but not limited to warranties of |
---|
25 | // merchantability or fitness for a particular purpose. |
---|
26 | // |
---|
27 | // Xilinx products are not intended for use in life support appliances, |
---|
28 | // devices, or systems. Use in such applications is expressly prohibited. |
---|
29 | // |
---|
30 | // Any modifications that are made to the source code are done at the user's |
---|
31 | // sole risk and will be unsupported. |
---|
32 | // |
---|
33 | // This copyright and support notice must be retained as part of this |
---|
34 | // text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
35 | // reserved. |
---|
36 | //----------------------------------------------------------------- |
---|
37 | |
---|
38 | //----------------------------------------------------------------- |
---|
39 | // System Generator version 10.1.3 VERILOG source file. |
---|
40 | // |
---|
41 | // Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
42 | // text/file contains proprietary, confidential information of Xilinx, |
---|
43 | // Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
44 | // copied and/or disclosed only pursuant to the terms of a valid license |
---|
45 | // agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
46 | // this text/file solely for design, simulation, implementation and |
---|
47 | // creation of design files limited to Xilinx devices or technologies. |
---|
48 | // Use with non-Xilinx devices or technologies is expressly prohibited |
---|
49 | // and immediately terminates your license unless covered by a separate |
---|
50 | // agreement. |
---|
51 | // |
---|
52 | // Xilinx is providing this design, code, or information "as is" solely |
---|
53 | // for use in developing programs and solutions for Xilinx devices. By |
---|
54 | // providing this design, code, or information as one possible |
---|
55 | // implementation of this feature, application or standard, Xilinx is |
---|
56 | // making no representation that this implementation is free from any |
---|
57 | // claims of infringement. You are responsible for obtaining any rights |
---|
58 | // you may require for your implementation. Xilinx expressly disclaims |
---|
59 | // any warranty whatsoever with respect to the adequacy of the |
---|
60 | // implementation, including but not limited to warranties of |
---|
61 | // merchantability or fitness for a particular purpose. |
---|
62 | // |
---|
63 | // Xilinx products are not intended for use in life support appliances, |
---|
64 | // devices, or systems. Use in such applications is expressly prohibited. |
---|
65 | // |
---|
66 | // Any modifications that are made to the source code are done at the user's |
---|
67 | // sole risk and will be unsupported. |
---|
68 | // |
---|
69 | // This copyright and support notice must be retained as part of this |
---|
70 | // text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
71 | // reserved. |
---|
72 | //----------------------------------------------------------------- |
---|
73 | // synopsys translate_off |
---|
74 | `ifndef simulating |
---|
75 | `define simulating 1 |
---|
76 | `endif |
---|
77 | // synopsys translate_on |
---|
78 | `ifndef simulating |
---|
79 | `define simulating 0 |
---|
80 | `endif |
---|
81 | `ifndef xlUnsigned |
---|
82 | `define xlUnsigned 1 |
---|
83 | `endif |
---|
84 | `ifndef xlSigned |
---|
85 | `define xlSigned 2 |
---|
86 | `endif |
---|
87 | `ifndef xlWrap |
---|
88 | `define xlWrap 1 |
---|
89 | `endif |
---|
90 | `ifndef xlSaturate |
---|
91 | `define xlSaturate 2 |
---|
92 | `endif |
---|
93 | `ifndef xlTruncate |
---|
94 | `define xlTruncate 1 |
---|
95 | `endif |
---|
96 | `ifndef xlRound |
---|
97 | `define xlRound 2 |
---|
98 | `endif |
---|
99 | `ifndef xlRoundBanker |
---|
100 | `define xlRoundBanker 3 |
---|
101 | `endif |
---|
102 | `ifndef xlAddMode |
---|
103 | `define xlAddMode 1 |
---|
104 | `endif |
---|
105 | `ifndef xlSubMode |
---|
106 | `define xlSubMode 2 |
---|
107 | `endif |
---|
108 | |
---|
109 | //----------------------------------------------------------------- |
---|
110 | // System Generator version 10.1.3 VERILOG source file. |
---|
111 | // |
---|
112 | // Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
113 | // text/file contains proprietary, confidential information of Xilinx, |
---|
114 | // Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
115 | // copied and/or disclosed only pursuant to the terms of a valid license |
---|
116 | // agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
117 | // this text/file solely for design, simulation, implementation and |
---|
118 | // creation of design files limited to Xilinx devices or technologies. |
---|
119 | // Use with non-Xilinx devices or technologies is expressly prohibited |
---|
120 | // and immediately terminates your license unless covered by a separate |
---|
121 | // agreement. |
---|
122 | // |
---|
123 | // Xilinx is providing this design, code, or information "as is" solely |
---|
124 | // for use in developing programs and solutions for Xilinx devices. By |
---|
125 | // providing this design, code, or information as one possible |
---|
126 | // implementation of this feature, application or standard, Xilinx is |
---|
127 | // making no representation that this implementation is free from any |
---|
128 | // claims of infringement. You are responsible for obtaining any rights |
---|
129 | // you may require for your implementation. Xilinx expressly disclaims |
---|
130 | // any warranty whatsoever with respect to the adequacy of the |
---|
131 | // implementation, including but not limited to warranties of |
---|
132 | // merchantability or fitness for a particular purpose. |
---|
133 | // |
---|
134 | // Xilinx products are not intended for use in life support appliances, |
---|
135 | // devices, or systems. Use in such applications is expressly prohibited. |
---|
136 | // |
---|
137 | // Any modifications that are made to the source code are done at the user's |
---|
138 | // sole risk and will be unsupported. |
---|
139 | // |
---|
140 | // This copyright and support notice must be retained as part of this |
---|
141 | // text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
142 | // reserved. |
---|
143 | //----------------------------------------------------------------- |
---|
144 | `timescale 1 ns / 10 ps |
---|
145 | module xlclkprobe (clk, clr, ce, fakeOutForXst); |
---|
146 | input clk; |
---|
147 | input clr; |
---|
148 | input ce; |
---|
149 | output fakeOutForXst; |
---|
150 | assign fakeOutForXst = 1'b0 ; |
---|
151 | //synopsys translate_off |
---|
152 | assign clock_pkg.int_clk = clk ; |
---|
153 | //synopsys translate_on |
---|
154 | endmodule |
---|
155 | |
---|
156 | //----------------------------------------------------------------- |
---|
157 | // System Generator version 10.1.3 VERILOG source file. |
---|
158 | // |
---|
159 | // Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
160 | // text/file contains proprietary, confidential information of Xilinx, |
---|
161 | // Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
162 | // copied and/or disclosed only pursuant to the terms of a valid license |
---|
163 | // agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
164 | // this text/file solely for design, simulation, implementation and |
---|
165 | // creation of design files limited to Xilinx devices or technologies. |
---|
166 | // Use with non-Xilinx devices or technologies is expressly prohibited |
---|
167 | // and immediately terminates your license unless covered by a separate |
---|
168 | // agreement. |
---|
169 | // |
---|
170 | // Xilinx is providing this design, code, or information "as is" solely |
---|
171 | // for use in developing programs and solutions for Xilinx devices. By |
---|
172 | // providing this design, code, or information as one possible |
---|
173 | // implementation of this feature, application or standard, Xilinx is |
---|
174 | // making no representation that this implementation is free from any |
---|
175 | // claims of infringement. You are responsible for obtaining any rights |
---|
176 | // you may require for your implementation. Xilinx expressly disclaims |
---|
177 | // any warranty whatsoever with respect to the adequacy of the |
---|
178 | // implementation, including but not limited to warranties of |
---|
179 | // merchantability or fitness for a particular purpose. |
---|
180 | // |
---|
181 | // Xilinx products are not intended for use in life support appliances, |
---|
182 | // devices, or systems. Use in such applications is expressly prohibited. |
---|
183 | // |
---|
184 | // Any modifications that are made to the source code are done at the user's |
---|
185 | // sole risk and will be unsupported. |
---|
186 | // |
---|
187 | // This copyright and support notice must be retained as part of this |
---|
188 | // text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
189 | // reserved. |
---|
190 | //----------------------------------------------------------------- |
---|
191 | `timescale 1 ns / 10 ps |
---|
192 | module xlclockdriver (sysclk, sysclr, sysce, clk, clr, ce); |
---|
193 | parameter signed [31:0] log_2_period = 1; |
---|
194 | parameter signed [31:0] period = 2; |
---|
195 | parameter signed [31:0] use_bufg = 1'b0; |
---|
196 | parameter signed [31:0] pipeline_regs = 5; |
---|
197 | |
---|
198 | input sysclk; |
---|
199 | input sysclr; |
---|
200 | input sysce; |
---|
201 | output clk; |
---|
202 | output clr; |
---|
203 | output ce; |
---|
204 | parameter signed [31:0] max_pipeline_regs = 8; |
---|
205 | parameter signed [31:0] num_pipeline_regs = (max_pipeline_regs > pipeline_regs)? pipeline_regs : max_pipeline_regs; |
---|
206 | parameter signed [31:0] factor = num_pipeline_regs/period; |
---|
207 | parameter signed [31:0] rem_pipeline_regs = num_pipeline_regs - (period * factor) + 1; |
---|
208 | parameter [log_2_period-1:0] trunc_period = ~period + 1; |
---|
209 | parameter signed [31:0] period_floor = (period>2)? period : 2; |
---|
210 | parameter signed [31:0] power_of_2_counter = (trunc_period == period) ? 1 : 0; |
---|
211 | parameter signed [31:0] cnt_width = (power_of_2_counter & (log_2_period>1)) ? (log_2_period - 1) : log_2_period; |
---|
212 | parameter [cnt_width-1:0] clk_for_ce_pulse_minus1 = period_floor-2; |
---|
213 | parameter [cnt_width-1:0] clk_for_ce_pulse_minus2 = (period-3>0)? period-3 : 0; |
---|
214 | parameter [cnt_width-1:0] clk_for_ce_pulse_minus_regs = ((period-rem_pipeline_regs)>0)? (period-rem_pipeline_regs) : 0; |
---|
215 | reg [cnt_width-1:0] clk_num; |
---|
216 | reg temp_ce_vec; |
---|
217 | (* MAX_FANOUT="REDUCE" *)wire [num_pipeline_regs:0] ce_vec /* synthesis MAX_FANOUT="REDUCE" */ ; |
---|
218 | wire internal_ce; |
---|
219 | reg cnt_clr; |
---|
220 | wire cnt_clr_dly; |
---|
221 | genvar index; |
---|
222 | initial |
---|
223 | begin |
---|
224 | clk_num = 'b0; |
---|
225 | end |
---|
226 | assign clk = sysclk ; |
---|
227 | assign clr = sysclr ; |
---|
228 | always @(posedge sysclk) |
---|
229 | begin : cntr_gen |
---|
230 | if ((cnt_clr_dly == 1'b1) || (sysclr == 1'b1)) |
---|
231 | begin:u1 |
---|
232 | clk_num = {cnt_width{1'b0}}; |
---|
233 | end |
---|
234 | else |
---|
235 | begin:u2 |
---|
236 | clk_num = clk_num + 1 ; |
---|
237 | end |
---|
238 | end |
---|
239 | generate |
---|
240 | if (power_of_2_counter == 1) |
---|
241 | begin:clr_gen_p2 |
---|
242 | always @(sysclr) |
---|
243 | begin:u1 |
---|
244 | cnt_clr = sysclr; |
---|
245 | end |
---|
246 | end |
---|
247 | endgenerate |
---|
248 | generate |
---|
249 | if (power_of_2_counter == 0) |
---|
250 | begin:clr_gen |
---|
251 | always @(clk_num or sysclr) |
---|
252 | begin:u1 |
---|
253 | if ( (clk_num == clk_for_ce_pulse_minus1) | (sysclr == 1'b1) ) |
---|
254 | begin:u2 |
---|
255 | cnt_clr = 1'b1 ; |
---|
256 | end |
---|
257 | else |
---|
258 | begin:u3 |
---|
259 | cnt_clr = 1'b0 ; |
---|
260 | end |
---|
261 | end |
---|
262 | end |
---|
263 | endgenerate |
---|
264 | synth_reg_w_init #(1, 0, 'b0000, 1) |
---|
265 | clr_reg(.i(cnt_clr), |
---|
266 | .ce(sysce), |
---|
267 | .clr(sysclr), |
---|
268 | .clk(sysclk), |
---|
269 | .o(cnt_clr_dly)); |
---|
270 | |
---|
271 | generate |
---|
272 | if (period > 1) |
---|
273 | begin:pipelined_ce |
---|
274 | always @(clk_num) |
---|
275 | begin:np_ce_gen |
---|
276 | if (clk_num == clk_for_ce_pulse_minus_regs) |
---|
277 | begin |
---|
278 | temp_ce_vec = 1'b1 ; |
---|
279 | end |
---|
280 | else |
---|
281 | begin |
---|
282 | temp_ce_vec = 1'b0 ; |
---|
283 | end |
---|
284 | end |
---|
285 | |
---|
286 | for(index=0; index<num_pipeline_regs; index=index+1) |
---|
287 | begin:ce_pipeline |
---|
288 | synth_reg_w_init #(1, ((((index+1)%period)>0)?0:1), 1'b0, 1) |
---|
289 | ce_reg(.i(ce_vec[index+1]), |
---|
290 | .ce(sysce), |
---|
291 | .clr(sysclr), |
---|
292 | .clk(sysclk), |
---|
293 | .o(ce_vec[index])); |
---|
294 | end |
---|
295 | assign ce_vec[num_pipeline_regs] = temp_ce_vec; |
---|
296 | assign internal_ce = ce_vec[0]; |
---|
297 | end |
---|
298 | endgenerate |
---|
299 | generate |
---|
300 | if (period > 1) |
---|
301 | begin:period_greater_than_1 |
---|
302 | if (use_bufg == 1'b1) |
---|
303 | begin:use_bufg |
---|
304 | BUFG ce_bufg_inst(.I(internal_ce), .O(ce)); |
---|
305 | end |
---|
306 | else |
---|
307 | begin:no_bufg |
---|
308 | assign ce = internal_ce; |
---|
309 | end |
---|
310 | end |
---|
311 | endgenerate |
---|
312 | |
---|
313 | generate |
---|
314 | if (period == 1) |
---|
315 | begin:period_1 |
---|
316 | assign ce = sysce; |
---|
317 | end |
---|
318 | endgenerate |
---|
319 | endmodule |
---|
320 | (* syn_noprune = "true" *) |
---|
321 | (* optimize_primitives = "false" *) |
---|
322 | (* dont_touch = "true" *) |
---|
323 | module default_clock_driver ( |
---|
324 | ce_1, |
---|
325 | ce_8, |
---|
326 | clk_1, |
---|
327 | clk_8, |
---|
328 | sysclk, |
---|
329 | sysce, |
---|
330 | sysce_clr |
---|
331 | ); |
---|
332 | |
---|
333 | input sysclk; |
---|
334 | input sysce; |
---|
335 | input sysce_clr; |
---|
336 | output ce_1; |
---|
337 | output ce_8; |
---|
338 | output clk_1; |
---|
339 | output clk_8; |
---|
340 | |
---|
341 | wire sysce_clr_x0; |
---|
342 | wire sysce_x0; |
---|
343 | wire sysclk_x0; |
---|
344 | wire xlclockdriver_1_ce; |
---|
345 | wire xlclockdriver_1_clk; |
---|
346 | wire xlclockdriver_8_ce; |
---|
347 | wire xlclockdriver_8_clk; |
---|
348 | |
---|
349 | assign ce_1 = xlclockdriver_1_ce; |
---|
350 | assign ce_8 = xlclockdriver_8_ce; |
---|
351 | assign clk_1 = xlclockdriver_1_clk; |
---|
352 | assign clk_8 = xlclockdriver_8_clk; |
---|
353 | assign sysclk_x0 = sysclk; |
---|
354 | assign sysce_x0 = sysce; |
---|
355 | assign sysce_clr_x0 = sysce_clr; |
---|
356 | |
---|
357 | |
---|
358 | xlclockdriver #( |
---|
359 | |
---|
360 | .log_2_period(1), |
---|
361 | .period(1), |
---|
362 | .use_bufg(0)) |
---|
363 | xlclockdriver_1 ( |
---|
364 | .sysce(sysce_x0), |
---|
365 | .sysclk(sysclk_x0), |
---|
366 | .sysclr(sysce_clr_x0), |
---|
367 | .ce(xlclockdriver_1_ce), |
---|
368 | .clk(xlclockdriver_1_clk) |
---|
369 | ); |
---|
370 | |
---|
371 | xlclockdriver #( |
---|
372 | |
---|
373 | .log_2_period(4), |
---|
374 | .period(8), |
---|
375 | .use_bufg(0)) |
---|
376 | xlclockdriver_8 ( |
---|
377 | .sysce(sysce_x0), |
---|
378 | .sysclk(sysclk_x0), |
---|
379 | .sysclr(sysce_clr_x0), |
---|
380 | .ce(xlclockdriver_8_ce), |
---|
381 | .clk(xlclockdriver_8_clk) |
---|
382 | ); |
---|
383 | endmodule |
---|
384 | module hex_out_cw ( |
---|
385 | clk,// clock period = 10.0 ns (100.0 Mhz) |
---|
386 | ce, |
---|
387 | address0, |
---|
388 | address1, |
---|
389 | divider, |
---|
390 | hex_l, |
---|
391 | hex_m, |
---|
392 | hex_r, |
---|
393 | led8, |
---|
394 | reset, |
---|
395 | scl, |
---|
396 | sda |
---|
397 | ); |
---|
398 | |
---|
399 | input clk;// clock period = 10.0 ns (100.0 Mhz) |
---|
400 | input ce; |
---|
401 | input [7:0] address0; |
---|
402 | input [7:0] address1; |
---|
403 | input [7:0] divider; |
---|
404 | input [7:0] hex_l; |
---|
405 | input [7:0] hex_m; |
---|
406 | input [7:0] hex_r; |
---|
407 | input [7:0] led8; |
---|
408 | input [0:0] reset; |
---|
409 | output [0:0] scl; |
---|
410 | output [0:0] sda; |
---|
411 | |
---|
412 | wire [7:0] address0_net; |
---|
413 | wire [7:0] address1_net; |
---|
414 | (* MAX_FANOUT="REDUCE" *) wire ce_1_sg_x10/* synthesis MAX_FANOUT="REDUCE" */; |
---|
415 | (* MAX_FANOUT="REDUCE" *) wire ce_8_sg_x2/* synthesis MAX_FANOUT="REDUCE" */; |
---|
416 | wire clkNet; |
---|
417 | wire clk_1_sg_x10; |
---|
418 | wire clk_8_sg_x2; |
---|
419 | wire [7:0] divider_net; |
---|
420 | wire [7:0] hex_l_net; |
---|
421 | wire [7:0] hex_m_net; |
---|
422 | wire [7:0] hex_r_net; |
---|
423 | wire [7:0] led8_net; |
---|
424 | (* syn_keep="true" *)(* keep="true" *)(* preserve_signal="true" *) wire persistentdff_inst_q/* synthesis syn_keep=1 keep=1 preserve_signal=1 */; |
---|
425 | wire [0:0] reset_net; |
---|
426 | wire [0:0] scl_net; |
---|
427 | wire [0:0] sda_net; |
---|
428 | |
---|
429 | assign clkNet = clk; |
---|
430 | assign address0_net = address0; |
---|
431 | assign address1_net = address1; |
---|
432 | assign divider_net = divider; |
---|
433 | assign hex_l_net = hex_l; |
---|
434 | assign hex_m_net = hex_m; |
---|
435 | assign hex_r_net = hex_r; |
---|
436 | assign led8_net = led8; |
---|
437 | assign reset_net = reset; |
---|
438 | assign scl = scl_net; |
---|
439 | assign sda = sda_net; |
---|
440 | |
---|
441 | |
---|
442 | default_clock_driver default_clock_driver_x0 ( |
---|
443 | .sysce(1'b1), |
---|
444 | .sysce_clr(1'b0), |
---|
445 | .sysclk(clkNet), |
---|
446 | .ce_1(ce_1_sg_x10), |
---|
447 | .ce_8(ce_8_sg_x2), |
---|
448 | .clk_1(clk_1_sg_x10), |
---|
449 | .clk_8(clk_8_sg_x2) |
---|
450 | ); |
---|
451 | |
---|
452 | hex_out hex_out_x0 ( |
---|
453 | .address0(address0_net), |
---|
454 | .address1(address1_net), |
---|
455 | .ce_1(ce_1_sg_x10), |
---|
456 | .ce_8(ce_8_sg_x2), |
---|
457 | .clk_1(clk_1_sg_x10), |
---|
458 | .clk_8(clk_8_sg_x2), |
---|
459 | .divider(divider_net), |
---|
460 | .hex_l(hex_l_net), |
---|
461 | .hex_m(hex_m_net), |
---|
462 | .hex_r(hex_r_net), |
---|
463 | .led8(led8_net), |
---|
464 | .reset(reset_net), |
---|
465 | .scl(scl_net), |
---|
466 | .sda(sda_net) |
---|
467 | ); |
---|
468 | |
---|
469 | xlclkprobe clk_probe ( |
---|
470 | .ce(1'b1), |
---|
471 | .clk(clkNet), |
---|
472 | .clr(1'b0) |
---|
473 | ); |
---|
474 | |
---|
475 | xlpersistentdff persistentdff_inst ( |
---|
476 | .clk(clkNet), |
---|
477 | .d(persistentdff_inst_q), |
---|
478 | .q(persistentdff_inst_q) |
---|
479 | ); |
---|
480 | endmodule |
---|
481 | |
---|
482 | module xlpersistentdff ( |
---|
483 | clk, |
---|
484 | d, |
---|
485 | q |
---|
486 | ); |
---|
487 | |
---|
488 | input clk; |
---|
489 | input d; |
---|
490 | output q; |
---|
491 | |
---|
492 | endmodule |
---|