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warp_v4_userio.vhd

Last change on this file was 1331, checked in by sgupta, 15 years ago
userio core for V4
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1	------------------------------------------------------------------------------
2	-- warp_v4_userio.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- ***************************************************************************
33	--
34	------------------------------------------------------------------------------
35	-- Filename: warp_v4_userio.vhd
36	-- Version: 1.00.a
37	-- Description: Top level design, instantiates library components and user logic.
38	-- Date: Mon Oct 5 10:19:40 2009 (by Create and Import Peripheral Wizard)
39	-- VHDL Standard: VHDL'93
40	------------------------------------------------------------------------------
41	-- Naming Conventions:
42	-- active low signals: "*_n"
43	-- clock signals: "clk", "clk_div#", "clk_#x"
44	-- reset signals: "rst", "rst_n"
45	-- generics: "C_*"
46	-- user defined types: "*_TYPE"
47	-- state machine next state: "*_ns"
48	-- state machine current state: "*_cs"
49	-- combinatorial signals: "*_com"
50	-- pipelined or register delay signals: "*_d#"
51	-- counter signals: "cnt"
52	-- clock enable signals: "*_ce"
53	-- internal version of output port: "*_i"
54	-- device pins: "*_pin"
55	-- ports: "- Names begin with Uppercase"
56	-- processes: "*_PROCESS"
57	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
58	------------------------------------------------------------------------------
59
60	library ieee;
61	use ieee.std_logic_1164.all;
62	use ieee.std_logic_arith.all;
63	use ieee.std_logic_unsigned.all;
64
65	library proc_common_v3_00_a;
66	use proc_common_v3_00_a.proc_common_pkg.all;
67	use proc_common_v3_00_a.ipif_pkg.all;
68	use proc_common_v3_00_a.soft_reset;
69
70	library plbv46_slave_single_v1_01_a;
71	use plbv46_slave_single_v1_01_a.plbv46_slave_single;
72
73	------------------------------------------------------------------------------
74	-- Entity section
75	------------------------------------------------------------------------------
76	-- Definition of Generics:
77	-- C_BASEADDR -- PLBv46 slave: base address
78	-- C_HIGHADDR -- PLBv46 slave: high address
79	-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
80	-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
81	-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
82	-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
83	-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
84	-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
85	-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
86	-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
87	-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
88	-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
89	-- C_FAMILY -- Xilinx FPGA family
90	--
91	-- Definition of Ports:
92	-- SPLB_Clk -- PLB main bus clock
93	-- SPLB_Rst -- PLB main bus reset
94	-- PLB_ABus -- PLB address bus
95	-- PLB_UABus -- PLB upper address bus
96	-- PLB_PAValid -- PLB primary address valid indicator
97	-- PLB_SAValid -- PLB secondary address valid indicator
98	-- PLB_rdPrim -- PLB secondary to primary read request indicator
99	-- PLB_wrPrim -- PLB secondary to primary write request indicator
100	-- PLB_masterID -- PLB current master identifier
101	-- PLB_abort -- PLB abort request indicator
102	-- PLB_busLock -- PLB bus lock
103	-- PLB_RNW -- PLB read/not write
104	-- PLB_BE -- PLB byte enables
105	-- PLB_MSize -- PLB master data bus size
106	-- PLB_size -- PLB transfer size
107	-- PLB_type -- PLB transfer type
108	-- PLB_lockErr -- PLB lock error indicator
109	-- PLB_wrDBus -- PLB write data bus
110	-- PLB_wrBurst -- PLB burst write transfer indicator
111	-- PLB_rdBurst -- PLB burst read transfer indicator
112	-- PLB_wrPendReq -- PLB write pending bus request indicator
113	-- PLB_rdPendReq -- PLB read pending bus request indicator
114	-- PLB_wrPendPri -- PLB write pending request priority
115	-- PLB_rdPendPri -- PLB read pending request priority
116	-- PLB_reqPri -- PLB current request priority
117	-- PLB_TAttribute -- PLB transfer attribute
118	-- Sl_addrAck -- Slave address acknowledge
119	-- Sl_SSize -- Slave data bus size
120	-- Sl_wait -- Slave wait indicator
121	-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
122	-- Sl_wrDAck -- Slave write data acknowledge
123	-- Sl_wrComp -- Slave write transfer complete indicator
124	-- Sl_wrBTerm -- Slave terminate write burst transfer
125	-- Sl_rdDBus -- Slave read data bus
126	-- Sl_rdWdAddr -- Slave read word address
127	-- Sl_rdDAck -- Slave read data acknowledge
128	-- Sl_rdComp -- Slave read transfer complete indicator
129	-- Sl_rdBTerm -- Slave terminate read burst transfer
130	-- Sl_MBusy -- Slave busy indicator
131	-- Sl_MWrErr -- Slave write error indicator
132	-- Sl_MRdErr -- Slave read error indicator
133	-- Sl_MIRQ -- Slave interrupt indicator
134	------------------------------------------------------------------------------
135
136	entity warp_v4_userio is
137	generic
138	(
139	-- ADD USER GENERICS BELOW THIS LINE ---------------
140	C_ADDRESS_0 : std_logic_vector := X"40";
141	C_ADDRESS_1 : std_logic_vector := X"50";
142	C_I2C_DIVIDER : std_logic_vector := X"40";
143	-- ADD USER GENERICS ABOVE THIS LINE ---------------
144
145	-- DO NOT EDIT BELOW THIS LINE ---------------------
146	-- Bus protocol parameters, do not add to or delete
147	C_BASEADDR : std_logic_vector := X"FFFFFFFF";
148	C_HIGHADDR : std_logic_vector := X"00000000";
149	C_SPLB_AWIDTH : integer := 32;
150	C_SPLB_DWIDTH : integer := 128;
151	C_SPLB_NUM_MASTERS : integer := 8;
152	C_SPLB_MID_WIDTH : integer := 3;
153	C_SPLB_NATIVE_DWIDTH : integer := 32;
154	C_SPLB_P2P : integer := 0;
155	C_SPLB_SUPPORT_BURSTS : integer := 0;
156	C_SPLB_SMALLEST_MASTER : integer := 32;
157	C_SPLB_CLK_PERIOD_PS : integer := 10000;
158	C_INCLUDE_DPHASE_TIMER : integer := 0;
159	C_FAMILY : string := "virtex5"
160	-- DO NOT EDIT ABOVE THIS LINE ---------------------
161	);
162	port
163	(
164	-- ADD USER PORTS BELOW THIS LINE ------------------
165	LEDs_out : out std_logic_vector(0 to 7);
166	IOEx_SDA : out std_logic;
167	IOEx_SCL : out std_logic;
168	PB_in : in std_logic_vector(0 to 3);
169	DIPSW_in : in std_logic_vector(0 to 3);
170	-- ADD USER PORTS ABOVE THIS LINE ------------------
171
172	-- DO NOT EDIT BELOW THIS LINE ---------------------
173	-- Bus protocol ports, do not add to or delete
174	SPLB_Clk : in std_logic;
175	SPLB_Rst : in std_logic;
176	PLB_ABus : in std_logic_vector(0 to 31);
177	PLB_UABus : in std_logic_vector(0 to 31);
178	PLB_PAValid : in std_logic;
179	PLB_SAValid : in std_logic;
180	PLB_rdPrim : in std_logic;
181	PLB_wrPrim : in std_logic;
182	PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
183	PLB_abort : in std_logic;
184	PLB_busLock : in std_logic;
185	PLB_RNW : in std_logic;
186	PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
187	PLB_MSize : in std_logic_vector(0 to 1);
188	PLB_size : in std_logic_vector(0 to 3);
189	PLB_type : in std_logic_vector(0 to 2);
190	PLB_lockErr : in std_logic;
191	PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
192	PLB_wrBurst : in std_logic;
193	PLB_rdBurst : in std_logic;
194	PLB_wrPendReq : in std_logic;
195	PLB_rdPendReq : in std_logic;
196	PLB_wrPendPri : in std_logic_vector(0 to 1);
197	PLB_rdPendPri : in std_logic_vector(0 to 1);
198	PLB_reqPri : in std_logic_vector(0 to 1);
199	PLB_TAttribute : in std_logic_vector(0 to 15);
200	Sl_addrAck : out std_logic;
201	Sl_SSize : out std_logic_vector(0 to 1);
202	Sl_wait : out std_logic;
203	Sl_rearbitrate : out std_logic;
204	Sl_wrDAck : out std_logic;
205	Sl_wrComp : out std_logic;
206	Sl_wrBTerm : out std_logic;
207	Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
208	Sl_rdWdAddr : out std_logic_vector(0 to 3);
209	Sl_rdDAck : out std_logic;
210	Sl_rdComp : out std_logic;
211	Sl_rdBTerm : out std_logic;
212	Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
213	Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
214	Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
215	Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
216	-- DO NOT EDIT ABOVE THIS LINE ---------------------
217	);
218
219	attribute SIGIS : string;
220	attribute SIGIS of SPLB_Clk : signal is "CLK";
221	attribute SIGIS of SPLB_Rst : signal is "RST";
222
223	end entity warp_v4_userio;
224
225	------------------------------------------------------------------------------
226	-- Architecture section
227	------------------------------------------------------------------------------
228
229	architecture IMP of warp_v4_userio is
230
231	-- constant ADDRESS0 : integer := C_ADDRESS_0;
232	-- constant ADDRESS1 : integer := C_ADDRESS_1;
233	-- constant I2C_DIVIDER : integer := C_I2C_DIVIDER;
234
235	------------------------------------------
236	-- Array of base/high address pairs for each address range
237	------------------------------------------
238	constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
239	constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
240	constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
241	constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
242	constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
243
244	constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
245	(
246	ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
247	ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
248	ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
249	ZERO_ADDR_PAD & RST_HIGHADDR -- soft reset space high address
250	);
251
252	------------------------------------------
253	-- Array of desired number of chip enables for each address range
254	------------------------------------------
255	constant USER_SLV_NUM_REG : integer := 5;
256	constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
257	constant RST_NUM_CE : integer := 1;
258
259	constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
260	(
261	0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
262	1 => RST_NUM_CE -- number of ce for soft reset space
263	);
264
265	------------------------------------------
266	-- Ratio of bus clock to core clock (for use in dual clock systems)
267	-- 1 = ratio is 1:1
268	-- 2 = ratio is 2:1
269	------------------------------------------
270	constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
271
272	------------------------------------------
273	-- Width of the slave data bus (32 only)
274	------------------------------------------
275	constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
276
277	constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
278
279	------------------------------------------
280	-- Width of triggered reset in bus clocks
281	------------------------------------------
282	constant RESET_WIDTH : integer := 4;
283
284	------------------------------------------
285	-- Index for CS/CE
286	------------------------------------------
287	constant USER_SLV_CS_INDEX : integer := 0;
288	constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
289	constant RST_CS_INDEX : integer := 1;
290	constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
291
292	constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
293
294	------------------------------------------
295	-- IP Interconnect (IPIC) signal declarations
296	------------------------------------------
297	signal ipif_Bus2IP_Clk : std_logic;
298	signal ipif_Bus2IP_Reset : std_logic;
299	signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
300	signal ipif_IP2Bus_WrAck : std_logic;
301	signal ipif_IP2Bus_RdAck : std_logic;
302	signal ipif_IP2Bus_Error : std_logic;
303	signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
304	signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
305	signal ipif_Bus2IP_RNW : std_logic;
306	signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
307	signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
308	signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
309	signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
310	signal rst_Bus2IP_Reset : std_logic;
311	signal rst_IP2Bus_WrAck : std_logic;
312	signal rst_IP2Bus_Error : std_logic;
313	signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
314	signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
315	signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
316	signal user_IP2Bus_RdAck : std_logic;
317	signal user_IP2Bus_WrAck : std_logic;
318	signal user_IP2Bus_Error : std_logic;
319
320	------------------------------------------
321	-- Component declaration for verilog user logic
322	------------------------------------------
323	component user_logic is
324	generic
325	(
326	C_ADDRESS_0 : std_logic_vector := X"40";
327	C_ADDRESS_1 : std_logic_vector := X"50";
328	C_I2C_DIVIDER : std_logic_vector := X"40";
329	C_SLV_DWIDTH : integer := 32;
330	C_NUM_REG : integer := 5
331	-- DO NOT EDIT ABOVE THIS LINE ---------------------
332	);
333	port
334	(
335	-- ADD USER PORTS BELOW THIS LINE ------------------
336	leds : out std_logic_vector(0 to 7);
337	hex_sda : out std_logic;
338	hex_scl : out std_logic;
339	pushbuttons : in std_logic_vector(0 to 3);
340	dipsw : in std_logic_vector(0 to 3);
341	-- ADD USER PORTS ABOVE THIS LINE ------------------
342
343	-- DO NOT EDIT BELOW THIS LINE ---------------------
344	-- Bus protocol ports, do not add to or delete
345	Bus2IP_Clk : in std_logic;
346	Bus2IP_Reset : in std_logic;
347	Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
348	Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
349	Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
350	Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
351	IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
352	IP2Bus_RdAck : out std_logic;
353	IP2Bus_WrAck : out std_logic;
354	IP2Bus_Error : out std_logic
355	-- DO NOT EDIT ABOVE THIS LINE ---------------------
356	);
357	end component user_logic;
358
359	begin
360
361	------------------------------------------
362	-- instantiate plbv46_slave_single
363	------------------------------------------
364	PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
365	generic map
366	(
367	C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
368	C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
369	C_SPLB_P2P => C_SPLB_P2P,
370	C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
371	C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
372	C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
373	C_SPLB_AWIDTH => C_SPLB_AWIDTH,
374	C_SPLB_DWIDTH => C_SPLB_DWIDTH,
375	C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
376	C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
377	C_FAMILY => C_FAMILY
378	)
379	port map
380	(
381	SPLB_Clk => SPLB_Clk,
382	SPLB_Rst => SPLB_Rst,
383	PLB_ABus => PLB_ABus,
384	PLB_UABus => PLB_UABus,
385	PLB_PAValid => PLB_PAValid,
386	PLB_SAValid => PLB_SAValid,
387	PLB_rdPrim => PLB_rdPrim,
388	PLB_wrPrim => PLB_wrPrim,
389	PLB_masterID => PLB_masterID,
390	PLB_abort => PLB_abort,
391	PLB_busLock => PLB_busLock,
392	PLB_RNW => PLB_RNW,
393	PLB_BE => PLB_BE,
394	PLB_MSize => PLB_MSize,
395	PLB_size => PLB_size,
396	PLB_type => PLB_type,
397	PLB_lockErr => PLB_lockErr,
398	PLB_wrDBus => PLB_wrDBus,
399	PLB_wrBurst => PLB_wrBurst,
400	PLB_rdBurst => PLB_rdBurst,
401	PLB_wrPendReq => PLB_wrPendReq,
402	PLB_rdPendReq => PLB_rdPendReq,
403	PLB_wrPendPri => PLB_wrPendPri,
404	PLB_rdPendPri => PLB_rdPendPri,
405	PLB_reqPri => PLB_reqPri,
406	PLB_TAttribute => PLB_TAttribute,
407	Sl_addrAck => Sl_addrAck,
408	Sl_SSize => Sl_SSize,
409	Sl_wait => Sl_wait,
410	Sl_rearbitrate => Sl_rearbitrate,
411	Sl_wrDAck => Sl_wrDAck,
412	Sl_wrComp => Sl_wrComp,
413	Sl_wrBTerm => Sl_wrBTerm,
414	Sl_rdDBus => Sl_rdDBus,
415	Sl_rdWdAddr => Sl_rdWdAddr,
416	Sl_rdDAck => Sl_rdDAck,
417	Sl_rdComp => Sl_rdComp,
418	Sl_rdBTerm => Sl_rdBTerm,
419	Sl_MBusy => Sl_MBusy,
420	Sl_MWrErr => Sl_MWrErr,
421	Sl_MRdErr => Sl_MRdErr,
422	Sl_MIRQ => Sl_MIRQ,
423	Bus2IP_Clk => ipif_Bus2IP_Clk,
424	Bus2IP_Reset => ipif_Bus2IP_Reset,
425	IP2Bus_Data => ipif_IP2Bus_Data,
426	IP2Bus_WrAck => ipif_IP2Bus_WrAck,
427	IP2Bus_RdAck => ipif_IP2Bus_RdAck,
428	IP2Bus_Error => ipif_IP2Bus_Error,
429	Bus2IP_Addr => ipif_Bus2IP_Addr,
430	Bus2IP_Data => ipif_Bus2IP_Data,
431	Bus2IP_RNW => ipif_Bus2IP_RNW,
432	Bus2IP_BE => ipif_Bus2IP_BE,
433	Bus2IP_CS => ipif_Bus2IP_CS,
434	Bus2IP_RdCE => ipif_Bus2IP_RdCE,
435	Bus2IP_WrCE => ipif_Bus2IP_WrCE
436	);
437
438	------------------------------------------
439	-- instantiate soft_reset
440	------------------------------------------
441	SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
442	generic map
443	(
444	C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
445	C_RESET_WIDTH => RESET_WIDTH
446	)
447	port map
448	(
449	Bus2IP_Reset => ipif_Bus2IP_Reset,
450	Bus2IP_Clk => ipif_Bus2IP_Clk,
451	Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
452	Bus2IP_Data => ipif_Bus2IP_Data,
453	Bus2IP_BE => ipif_Bus2IP_BE,
454	Reset2IP_Reset => rst_Bus2IP_Reset,
455	Reset2Bus_WrAck => rst_IP2Bus_WrAck,
456	Reset2Bus_Error => rst_IP2Bus_Error,
457	Reset2Bus_ToutSup => open
458	);
459
460	------------------------------------------
461	-- instantiate User Logic
462	------------------------------------------
463	USER_LOGIC_I : component user_logic
464	generic map
465	(
466	-- MAP USER GENERICS BELOW THIS LINE ---------------
467	C_ADDRESS_0 => C_ADDRESS_0,
468	C_ADDRESS_1 => C_ADDRESS_1,
469	C_I2C_DIVIDER => C_I2C_DIVIDER,
470	-- MAP USER GENERICS ABOVE THIS LINE ---------------
471
472	C_SLV_DWIDTH => USER_SLV_DWIDTH,
473	C_NUM_REG => USER_NUM_REG
474	)
475	port map
476	(
477	-- MAP USER PORTS BELOW THIS LINE ------------------
478	leds => LEDs_out,
479	hex_sda => IOEx_SDA,
480	hex_scl => IOEx_SCL,
481	pushbuttons => PB_in,
482	dipsw => DIPSW_in,
483	-- MAP USER PORTS ABOVE THIS LINE ------------------
484
485	Bus2IP_Clk => ipif_Bus2IP_Clk,
486	Bus2IP_Reset => rst_Bus2IP_Reset,
487	Bus2IP_Data => ipif_Bus2IP_Data,
488	Bus2IP_BE => ipif_Bus2IP_BE,
489	Bus2IP_RdCE => user_Bus2IP_RdCE,
490	Bus2IP_WrCE => user_Bus2IP_WrCE,
491	IP2Bus_Data => user_IP2Bus_Data,
492	IP2Bus_RdAck => user_IP2Bus_RdAck,
493	IP2Bus_WrAck => user_IP2Bus_WrAck,
494	IP2Bus_Error => user_IP2Bus_Error
495	);
496
497	------------------------------------------
498	-- connect internal signals
499	------------------------------------------
500	IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
501	begin
502
503	case ipif_Bus2IP_CS is
504	when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
505	when "01" => ipif_IP2Bus_Data <= (others => '0');
506	when others => ipif_IP2Bus_Data <= (others => '0');
507	end case;
508
509	end process IP2BUS_DATA_MUX_PROC;
510
511	ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
512	ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
513	ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
514
515	user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
516	user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
517
518	end IMP;

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source: PlatformSupport/CustomPeripherals/pcores/warp_v4_userio_v1_00_a/hdl/vhdl/warp_v4_userio.vhd

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