[1331] | 1 | ------------------------------------------------------------------------------ |
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| 2 | -- warp_v4_userio.vhd - entity/architecture pair |
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| 3 | ------------------------------------------------------------------------------ |
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| 4 | -- IMPORTANT: |
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| 5 | -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. |
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| 6 | -- |
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| 7 | -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. |
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| 8 | -- |
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| 9 | -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW |
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| 10 | -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION |
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| 11 | -- OF THE USER_LOGIC ENTITY. |
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| 12 | ------------------------------------------------------------------------------ |
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| 13 | -- |
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| 14 | -- *************************************************************************** |
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| 15 | -- ** Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. ** |
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| 16 | -- ** ** |
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| 17 | -- ** Xilinx, Inc. ** |
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| 18 | -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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| 19 | -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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| 20 | -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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| 21 | -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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| 22 | -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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| 23 | -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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| 24 | -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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| 25 | -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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| 26 | -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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| 27 | -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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| 28 | -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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| 29 | -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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| 30 | -- ** FOR A PARTICULAR PURPOSE. ** |
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| 31 | -- ** ** |
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| 32 | -- *************************************************************************** |
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| 33 | -- |
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| 34 | ------------------------------------------------------------------------------ |
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| 35 | -- Filename: warp_v4_userio.vhd |
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| 36 | -- Version: 1.00.a |
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| 37 | -- Description: Top level design, instantiates library components and user logic. |
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| 38 | -- Date: Mon Oct 5 10:19:40 2009 (by Create and Import Peripheral Wizard) |
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| 39 | -- VHDL Standard: VHDL'93 |
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| 40 | ------------------------------------------------------------------------------ |
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| 41 | -- Naming Conventions: |
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| 42 | -- active low signals: "*_n" |
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| 43 | -- clock signals: "clk", "clk_div#", "clk_#x" |
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| 44 | -- reset signals: "rst", "rst_n" |
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| 45 | -- generics: "C_*" |
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| 46 | -- user defined types: "*_TYPE" |
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| 47 | -- state machine next state: "*_ns" |
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| 48 | -- state machine current state: "*_cs" |
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| 49 | -- combinatorial signals: "*_com" |
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| 50 | -- pipelined or register delay signals: "*_d#" |
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| 51 | -- counter signals: "*cnt*" |
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| 52 | -- clock enable signals: "*_ce" |
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| 53 | -- internal version of output port: "*_i" |
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| 54 | -- device pins: "*_pin" |
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| 55 | -- ports: "- Names begin with Uppercase" |
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| 56 | -- processes: "*_PROCESS" |
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| 57 | -- component instantiations: "<ENTITY_>I_<#|FUNC>" |
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| 58 | ------------------------------------------------------------------------------ |
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| 59 | |
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| 60 | library ieee; |
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| 61 | use ieee.std_logic_1164.all; |
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| 62 | use ieee.std_logic_arith.all; |
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| 63 | use ieee.std_logic_unsigned.all; |
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| 64 | |
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| 65 | library proc_common_v3_00_a; |
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| 66 | use proc_common_v3_00_a.proc_common_pkg.all; |
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| 67 | use proc_common_v3_00_a.ipif_pkg.all; |
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| 68 | use proc_common_v3_00_a.soft_reset; |
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| 69 | |
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| 70 | library plbv46_slave_single_v1_01_a; |
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| 71 | use plbv46_slave_single_v1_01_a.plbv46_slave_single; |
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| 72 | |
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| 73 | ------------------------------------------------------------------------------ |
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| 74 | -- Entity section |
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| 75 | ------------------------------------------------------------------------------ |
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| 76 | -- Definition of Generics: |
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| 77 | -- C_BASEADDR -- PLBv46 slave: base address |
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| 78 | -- C_HIGHADDR -- PLBv46 slave: high address |
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| 79 | -- C_SPLB_AWIDTH -- PLBv46 slave: address bus width |
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| 80 | -- C_SPLB_DWIDTH -- PLBv46 slave: data bus width |
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| 81 | -- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters |
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| 82 | -- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width |
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| 83 | -- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width |
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| 84 | -- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme |
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| 85 | -- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts |
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| 86 | -- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master |
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| 87 | -- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds |
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| 88 | -- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer |
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| 89 | -- C_FAMILY -- Xilinx FPGA family |
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| 90 | -- |
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| 91 | -- Definition of Ports: |
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| 92 | -- SPLB_Clk -- PLB main bus clock |
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| 93 | -- SPLB_Rst -- PLB main bus reset |
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| 94 | -- PLB_ABus -- PLB address bus |
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| 95 | -- PLB_UABus -- PLB upper address bus |
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| 96 | -- PLB_PAValid -- PLB primary address valid indicator |
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| 97 | -- PLB_SAValid -- PLB secondary address valid indicator |
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| 98 | -- PLB_rdPrim -- PLB secondary to primary read request indicator |
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| 99 | -- PLB_wrPrim -- PLB secondary to primary write request indicator |
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| 100 | -- PLB_masterID -- PLB current master identifier |
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| 101 | -- PLB_abort -- PLB abort request indicator |
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| 102 | -- PLB_busLock -- PLB bus lock |
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| 103 | -- PLB_RNW -- PLB read/not write |
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| 104 | -- PLB_BE -- PLB byte enables |
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| 105 | -- PLB_MSize -- PLB master data bus size |
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| 106 | -- PLB_size -- PLB transfer size |
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| 107 | -- PLB_type -- PLB transfer type |
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| 108 | -- PLB_lockErr -- PLB lock error indicator |
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| 109 | -- PLB_wrDBus -- PLB write data bus |
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| 110 | -- PLB_wrBurst -- PLB burst write transfer indicator |
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| 111 | -- PLB_rdBurst -- PLB burst read transfer indicator |
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| 112 | -- PLB_wrPendReq -- PLB write pending bus request indicator |
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| 113 | -- PLB_rdPendReq -- PLB read pending bus request indicator |
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| 114 | -- PLB_wrPendPri -- PLB write pending request priority |
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| 115 | -- PLB_rdPendPri -- PLB read pending request priority |
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| 116 | -- PLB_reqPri -- PLB current request priority |
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| 117 | -- PLB_TAttribute -- PLB transfer attribute |
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| 118 | -- Sl_addrAck -- Slave address acknowledge |
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| 119 | -- Sl_SSize -- Slave data bus size |
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| 120 | -- Sl_wait -- Slave wait indicator |
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| 121 | -- Sl_rearbitrate -- Slave re-arbitrate bus indicator |
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| 122 | -- Sl_wrDAck -- Slave write data acknowledge |
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| 123 | -- Sl_wrComp -- Slave write transfer complete indicator |
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| 124 | -- Sl_wrBTerm -- Slave terminate write burst transfer |
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| 125 | -- Sl_rdDBus -- Slave read data bus |
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| 126 | -- Sl_rdWdAddr -- Slave read word address |
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| 127 | -- Sl_rdDAck -- Slave read data acknowledge |
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| 128 | -- Sl_rdComp -- Slave read transfer complete indicator |
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| 129 | -- Sl_rdBTerm -- Slave terminate read burst transfer |
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| 130 | -- Sl_MBusy -- Slave busy indicator |
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| 131 | -- Sl_MWrErr -- Slave write error indicator |
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| 132 | -- Sl_MRdErr -- Slave read error indicator |
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| 133 | -- Sl_MIRQ -- Slave interrupt indicator |
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| 134 | ------------------------------------------------------------------------------ |
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| 135 | |
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| 136 | entity warp_v4_userio is |
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| 137 | generic |
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| 138 | ( |
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| 139 | -- ADD USER GENERICS BELOW THIS LINE --------------- |
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| 140 | C_ADDRESS_0 : std_logic_vector := X"40"; |
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| 141 | C_ADDRESS_1 : std_logic_vector := X"50"; |
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| 142 | C_I2C_DIVIDER : std_logic_vector := X"40"; |
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| 143 | -- ADD USER GENERICS ABOVE THIS LINE --------------- |
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| 144 | |
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| 145 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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| 146 | -- Bus protocol parameters, do not add to or delete |
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| 147 | C_BASEADDR : std_logic_vector := X"FFFFFFFF"; |
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| 148 | C_HIGHADDR : std_logic_vector := X"00000000"; |
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| 149 | C_SPLB_AWIDTH : integer := 32; |
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| 150 | C_SPLB_DWIDTH : integer := 128; |
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| 151 | C_SPLB_NUM_MASTERS : integer := 8; |
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| 152 | C_SPLB_MID_WIDTH : integer := 3; |
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| 153 | C_SPLB_NATIVE_DWIDTH : integer := 32; |
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| 154 | C_SPLB_P2P : integer := 0; |
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| 155 | C_SPLB_SUPPORT_BURSTS : integer := 0; |
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| 156 | C_SPLB_SMALLEST_MASTER : integer := 32; |
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| 157 | C_SPLB_CLK_PERIOD_PS : integer := 10000; |
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| 158 | C_INCLUDE_DPHASE_TIMER : integer := 0; |
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| 159 | C_FAMILY : string := "virtex5" |
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| 160 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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| 161 | ); |
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| 162 | port |
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| 163 | ( |
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| 164 | -- ADD USER PORTS BELOW THIS LINE ------------------ |
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| 165 | LEDs_out : out std_logic_vector(0 to 7); |
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| 166 | IOEx_SDA : out std_logic; |
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| 167 | IOEx_SCL : out std_logic; |
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| 168 | PB_in : in std_logic_vector(0 to 3); |
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| 169 | DIPSW_in : in std_logic_vector(0 to 3); |
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| 170 | -- ADD USER PORTS ABOVE THIS LINE ------------------ |
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| 171 | |
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| 172 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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| 173 | -- Bus protocol ports, do not add to or delete |
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| 174 | SPLB_Clk : in std_logic; |
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| 175 | SPLB_Rst : in std_logic; |
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| 176 | PLB_ABus : in std_logic_vector(0 to 31); |
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| 177 | PLB_UABus : in std_logic_vector(0 to 31); |
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| 178 | PLB_PAValid : in std_logic; |
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| 179 | PLB_SAValid : in std_logic; |
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| 180 | PLB_rdPrim : in std_logic; |
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| 181 | PLB_wrPrim : in std_logic; |
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| 182 | PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1); |
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| 183 | PLB_abort : in std_logic; |
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| 184 | PLB_busLock : in std_logic; |
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| 185 | PLB_RNW : in std_logic; |
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| 186 | PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1); |
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| 187 | PLB_MSize : in std_logic_vector(0 to 1); |
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| 188 | PLB_size : in std_logic_vector(0 to 3); |
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| 189 | PLB_type : in std_logic_vector(0 to 2); |
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| 190 | PLB_lockErr : in std_logic; |
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| 191 | PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); |
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| 192 | PLB_wrBurst : in std_logic; |
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| 193 | PLB_rdBurst : in std_logic; |
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| 194 | PLB_wrPendReq : in std_logic; |
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| 195 | PLB_rdPendReq : in std_logic; |
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| 196 | PLB_wrPendPri : in std_logic_vector(0 to 1); |
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| 197 | PLB_rdPendPri : in std_logic_vector(0 to 1); |
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| 198 | PLB_reqPri : in std_logic_vector(0 to 1); |
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| 199 | PLB_TAttribute : in std_logic_vector(0 to 15); |
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| 200 | Sl_addrAck : out std_logic; |
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| 201 | Sl_SSize : out std_logic_vector(0 to 1); |
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| 202 | Sl_wait : out std_logic; |
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| 203 | Sl_rearbitrate : out std_logic; |
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| 204 | Sl_wrDAck : out std_logic; |
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| 205 | Sl_wrComp : out std_logic; |
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| 206 | Sl_wrBTerm : out std_logic; |
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| 207 | Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); |
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| 208 | Sl_rdWdAddr : out std_logic_vector(0 to 3); |
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| 209 | Sl_rdDAck : out std_logic; |
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| 210 | Sl_rdComp : out std_logic; |
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| 211 | Sl_rdBTerm : out std_logic; |
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| 212 | Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); |
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| 213 | Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); |
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| 214 | Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); |
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| 215 | Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1) |
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| 216 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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| 217 | ); |
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| 218 | |
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| 219 | attribute SIGIS : string; |
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| 220 | attribute SIGIS of SPLB_Clk : signal is "CLK"; |
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| 221 | attribute SIGIS of SPLB_Rst : signal is "RST"; |
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| 222 | |
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| 223 | end entity warp_v4_userio; |
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| 224 | |
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| 225 | ------------------------------------------------------------------------------ |
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| 226 | -- Architecture section |
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| 227 | ------------------------------------------------------------------------------ |
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| 228 | |
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| 229 | architecture IMP of warp_v4_userio is |
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| 230 | |
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| 231 | -- constant ADDRESS0 : integer := C_ADDRESS_0; |
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| 232 | -- constant ADDRESS1 : integer := C_ADDRESS_1; |
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| 233 | -- constant I2C_DIVIDER : integer := C_I2C_DIVIDER; |
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| 234 | |
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| 235 | ------------------------------------------ |
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| 236 | -- Array of base/high address pairs for each address range |
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| 237 | ------------------------------------------ |
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| 238 | constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); |
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| 239 | constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000"; |
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| 240 | constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF"; |
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| 241 | constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100"; |
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| 242 | constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF"; |
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| 243 | |
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| 244 | constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := |
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| 245 | ( |
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| 246 | ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address |
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| 247 | ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address |
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| 248 | ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address |
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| 249 | ZERO_ADDR_PAD & RST_HIGHADDR -- soft reset space high address |
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| 250 | ); |
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| 251 | |
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| 252 | ------------------------------------------ |
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| 253 | -- Array of desired number of chip enables for each address range |
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| 254 | ------------------------------------------ |
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| 255 | constant USER_SLV_NUM_REG : integer := 5; |
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| 256 | constant USER_NUM_REG : integer := USER_SLV_NUM_REG; |
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| 257 | constant RST_NUM_CE : integer := 1; |
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| 258 | |
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| 259 | constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := |
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| 260 | ( |
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| 261 | 0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space |
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| 262 | 1 => RST_NUM_CE -- number of ce for soft reset space |
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| 263 | ); |
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| 264 | |
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| 265 | ------------------------------------------ |
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| 266 | -- Ratio of bus clock to core clock (for use in dual clock systems) |
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| 267 | -- 1 = ratio is 1:1 |
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| 268 | -- 2 = ratio is 2:1 |
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| 269 | ------------------------------------------ |
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| 270 | constant IPIF_BUS2CORE_CLK_RATIO : integer := 1; |
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| 271 | |
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| 272 | ------------------------------------------ |
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| 273 | -- Width of the slave data bus (32 only) |
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| 274 | ------------------------------------------ |
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| 275 | constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; |
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| 276 | |
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| 277 | constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; |
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| 278 | |
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| 279 | ------------------------------------------ |
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| 280 | -- Width of triggered reset in bus clocks |
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| 281 | ------------------------------------------ |
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| 282 | constant RESET_WIDTH : integer := 4; |
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| 283 | |
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| 284 | ------------------------------------------ |
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| 285 | -- Index for CS/CE |
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| 286 | ------------------------------------------ |
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| 287 | constant USER_SLV_CS_INDEX : integer := 0; |
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| 288 | constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); |
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| 289 | constant RST_CS_INDEX : integer := 1; |
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| 290 | constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX); |
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| 291 | |
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| 292 | constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; |
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| 293 | |
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| 294 | ------------------------------------------ |
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| 295 | -- IP Interconnect (IPIC) signal declarations |
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| 296 | ------------------------------------------ |
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| 297 | signal ipif_Bus2IP_Clk : std_logic; |
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| 298 | signal ipif_Bus2IP_Reset : std_logic; |
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| 299 | signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); |
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| 300 | signal ipif_IP2Bus_WrAck : std_logic; |
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| 301 | signal ipif_IP2Bus_RdAck : std_logic; |
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| 302 | signal ipif_IP2Bus_Error : std_logic; |
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| 303 | signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1); |
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| 304 | signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); |
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| 305 | signal ipif_Bus2IP_RNW : std_logic; |
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| 306 | signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1); |
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| 307 | signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1); |
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| 308 | signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); |
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| 309 | signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); |
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| 310 | signal rst_Bus2IP_Reset : std_logic; |
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| 311 | signal rst_IP2Bus_WrAck : std_logic; |
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| 312 | signal rst_IP2Bus_Error : std_logic; |
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| 313 | signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1); |
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| 314 | signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1); |
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| 315 | signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1); |
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| 316 | signal user_IP2Bus_RdAck : std_logic; |
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| 317 | signal user_IP2Bus_WrAck : std_logic; |
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| 318 | signal user_IP2Bus_Error : std_logic; |
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| 319 | |
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| 320 | ------------------------------------------ |
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| 321 | -- Component declaration for verilog user logic |
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| 322 | ------------------------------------------ |
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| 323 | component user_logic is |
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| 324 | generic |
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| 325 | ( |
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| 326 | C_ADDRESS_0 : std_logic_vector := X"40"; |
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| 327 | C_ADDRESS_1 : std_logic_vector := X"50"; |
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| 328 | C_I2C_DIVIDER : std_logic_vector := X"40"; |
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| 329 | C_SLV_DWIDTH : integer := 32; |
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| 330 | C_NUM_REG : integer := 5 |
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| 331 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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| 332 | ); |
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| 333 | port |
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| 334 | ( |
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| 335 | -- ADD USER PORTS BELOW THIS LINE ------------------ |
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| 336 | leds : out std_logic_vector(0 to 7); |
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| 337 | hex_sda : out std_logic; |
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| 338 | hex_scl : out std_logic; |
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| 339 | pushbuttons : in std_logic_vector(0 to 3); |
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| 340 | dipsw : in std_logic_vector(0 to 3); |
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| 341 | -- ADD USER PORTS ABOVE THIS LINE ------------------ |
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| 342 | |
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| 343 | -- DO NOT EDIT BELOW THIS LINE --------------------- |
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| 344 | -- Bus protocol ports, do not add to or delete |
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| 345 | Bus2IP_Clk : in std_logic; |
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| 346 | Bus2IP_Reset : in std_logic; |
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| 347 | Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1); |
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| 348 | Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1); |
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| 349 | Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1); |
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| 350 | Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1); |
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| 351 | IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1); |
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| 352 | IP2Bus_RdAck : out std_logic; |
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| 353 | IP2Bus_WrAck : out std_logic; |
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| 354 | IP2Bus_Error : out std_logic |
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| 355 | -- DO NOT EDIT ABOVE THIS LINE --------------------- |
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| 356 | ); |
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| 357 | end component user_logic; |
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| 358 | |
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| 359 | begin |
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| 360 | |
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| 361 | ------------------------------------------ |
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| 362 | -- instantiate plbv46_slave_single |
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| 363 | ------------------------------------------ |
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| 364 | PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single |
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| 365 | generic map |
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| 366 | ( |
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| 367 | C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, |
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| 368 | C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, |
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| 369 | C_SPLB_P2P => C_SPLB_P2P, |
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| 370 | C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO, |
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| 371 | C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH, |
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| 372 | C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS, |
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| 373 | C_SPLB_AWIDTH => C_SPLB_AWIDTH, |
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| 374 | C_SPLB_DWIDTH => C_SPLB_DWIDTH, |
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| 375 | C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, |
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| 376 | C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER, |
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| 377 | C_FAMILY => C_FAMILY |
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| 378 | ) |
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| 379 | port map |
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| 380 | ( |
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| 381 | SPLB_Clk => SPLB_Clk, |
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| 382 | SPLB_Rst => SPLB_Rst, |
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| 383 | PLB_ABus => PLB_ABus, |
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| 384 | PLB_UABus => PLB_UABus, |
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| 385 | PLB_PAValid => PLB_PAValid, |
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| 386 | PLB_SAValid => PLB_SAValid, |
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| 387 | PLB_rdPrim => PLB_rdPrim, |
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| 388 | PLB_wrPrim => PLB_wrPrim, |
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| 389 | PLB_masterID => PLB_masterID, |
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| 390 | PLB_abort => PLB_abort, |
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| 391 | PLB_busLock => PLB_busLock, |
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| 392 | PLB_RNW => PLB_RNW, |
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| 393 | PLB_BE => PLB_BE, |
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| 394 | PLB_MSize => PLB_MSize, |
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| 395 | PLB_size => PLB_size, |
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| 396 | PLB_type => PLB_type, |
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| 397 | PLB_lockErr => PLB_lockErr, |
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| 398 | PLB_wrDBus => PLB_wrDBus, |
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| 399 | PLB_wrBurst => PLB_wrBurst, |
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| 400 | PLB_rdBurst => PLB_rdBurst, |
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| 401 | PLB_wrPendReq => PLB_wrPendReq, |
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| 402 | PLB_rdPendReq => PLB_rdPendReq, |
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| 403 | PLB_wrPendPri => PLB_wrPendPri, |
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| 404 | PLB_rdPendPri => PLB_rdPendPri, |
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| 405 | PLB_reqPri => PLB_reqPri, |
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| 406 | PLB_TAttribute => PLB_TAttribute, |
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| 407 | Sl_addrAck => Sl_addrAck, |
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| 408 | Sl_SSize => Sl_SSize, |
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| 409 | Sl_wait => Sl_wait, |
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| 410 | Sl_rearbitrate => Sl_rearbitrate, |
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| 411 | Sl_wrDAck => Sl_wrDAck, |
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| 412 | Sl_wrComp => Sl_wrComp, |
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| 413 | Sl_wrBTerm => Sl_wrBTerm, |
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| 414 | Sl_rdDBus => Sl_rdDBus, |
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| 415 | Sl_rdWdAddr => Sl_rdWdAddr, |
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| 416 | Sl_rdDAck => Sl_rdDAck, |
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| 417 | Sl_rdComp => Sl_rdComp, |
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| 418 | Sl_rdBTerm => Sl_rdBTerm, |
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| 419 | Sl_MBusy => Sl_MBusy, |
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| 420 | Sl_MWrErr => Sl_MWrErr, |
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| 421 | Sl_MRdErr => Sl_MRdErr, |
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| 422 | Sl_MIRQ => Sl_MIRQ, |
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| 423 | Bus2IP_Clk => ipif_Bus2IP_Clk, |
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| 424 | Bus2IP_Reset => ipif_Bus2IP_Reset, |
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| 425 | IP2Bus_Data => ipif_IP2Bus_Data, |
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| 426 | IP2Bus_WrAck => ipif_IP2Bus_WrAck, |
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| 427 | IP2Bus_RdAck => ipif_IP2Bus_RdAck, |
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| 428 | IP2Bus_Error => ipif_IP2Bus_Error, |
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| 429 | Bus2IP_Addr => ipif_Bus2IP_Addr, |
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| 430 | Bus2IP_Data => ipif_Bus2IP_Data, |
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| 431 | Bus2IP_RNW => ipif_Bus2IP_RNW, |
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| 432 | Bus2IP_BE => ipif_Bus2IP_BE, |
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| 433 | Bus2IP_CS => ipif_Bus2IP_CS, |
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| 434 | Bus2IP_RdCE => ipif_Bus2IP_RdCE, |
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| 435 | Bus2IP_WrCE => ipif_Bus2IP_WrCE |
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| 436 | ); |
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| 437 | |
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| 438 | ------------------------------------------ |
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| 439 | -- instantiate soft_reset |
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| 440 | ------------------------------------------ |
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| 441 | SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset |
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| 442 | generic map |
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| 443 | ( |
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| 444 | C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, |
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| 445 | C_RESET_WIDTH => RESET_WIDTH |
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| 446 | ) |
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| 447 | port map |
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| 448 | ( |
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| 449 | Bus2IP_Reset => ipif_Bus2IP_Reset, |
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| 450 | Bus2IP_Clk => ipif_Bus2IP_Clk, |
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| 451 | Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX), |
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| 452 | Bus2IP_Data => ipif_Bus2IP_Data, |
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| 453 | Bus2IP_BE => ipif_Bus2IP_BE, |
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| 454 | Reset2IP_Reset => rst_Bus2IP_Reset, |
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| 455 | Reset2Bus_WrAck => rst_IP2Bus_WrAck, |
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| 456 | Reset2Bus_Error => rst_IP2Bus_Error, |
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| 457 | Reset2Bus_ToutSup => open |
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| 458 | ); |
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| 459 | |
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| 460 | ------------------------------------------ |
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| 461 | -- instantiate User Logic |
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| 462 | ------------------------------------------ |
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| 463 | USER_LOGIC_I : component user_logic |
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| 464 | generic map |
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| 465 | ( |
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| 466 | -- MAP USER GENERICS BELOW THIS LINE --------------- |
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| 467 | C_ADDRESS_0 => C_ADDRESS_0, |
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| 468 | C_ADDRESS_1 => C_ADDRESS_1, |
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| 469 | C_I2C_DIVIDER => C_I2C_DIVIDER, |
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| 470 | -- MAP USER GENERICS ABOVE THIS LINE --------------- |
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| 471 | |
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| 472 | C_SLV_DWIDTH => USER_SLV_DWIDTH, |
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| 473 | C_NUM_REG => USER_NUM_REG |
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| 474 | ) |
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| 475 | port map |
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| 476 | ( |
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| 477 | -- MAP USER PORTS BELOW THIS LINE ------------------ |
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| 478 | leds => LEDs_out, |
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| 479 | hex_sda => IOEx_SDA, |
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| 480 | hex_scl => IOEx_SCL, |
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| 481 | pushbuttons => PB_in, |
---|
| 482 | dipsw => DIPSW_in, |
---|
| 483 | -- MAP USER PORTS ABOVE THIS LINE ------------------ |
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| 484 | |
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| 485 | Bus2IP_Clk => ipif_Bus2IP_Clk, |
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| 486 | Bus2IP_Reset => rst_Bus2IP_Reset, |
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| 487 | Bus2IP_Data => ipif_Bus2IP_Data, |
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| 488 | Bus2IP_BE => ipif_Bus2IP_BE, |
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| 489 | Bus2IP_RdCE => user_Bus2IP_RdCE, |
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| 490 | Bus2IP_WrCE => user_Bus2IP_WrCE, |
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| 491 | IP2Bus_Data => user_IP2Bus_Data, |
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| 492 | IP2Bus_RdAck => user_IP2Bus_RdAck, |
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| 493 | IP2Bus_WrAck => user_IP2Bus_WrAck, |
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| 494 | IP2Bus_Error => user_IP2Bus_Error |
---|
| 495 | ); |
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| 496 | |
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| 497 | ------------------------------------------ |
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| 498 | -- connect internal signals |
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| 499 | ------------------------------------------ |
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| 500 | IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is |
---|
| 501 | begin |
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| 502 | |
---|
| 503 | case ipif_Bus2IP_CS is |
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| 504 | when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data; |
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| 505 | when "01" => ipif_IP2Bus_Data <= (others => '0'); |
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| 506 | when others => ipif_IP2Bus_Data <= (others => '0'); |
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| 507 | end case; |
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| 508 | |
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| 509 | end process IP2BUS_DATA_MUX_PROC; |
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| 510 | |
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| 511 | ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck; |
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| 512 | ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; |
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| 513 | ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error; |
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| 514 | |
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| 515 | user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); |
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| 516 | user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); |
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| 517 | |
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| 518 | end IMP; |
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