[1331] | 1 | (edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) |
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| 2 | (status (written (timeStamp 2009 10 1 13 35 22) |
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| 3 | (author "Xilinx, Inc.") |
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| 4 | (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 10.1.03; Cores Update # 3")))) |
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| 5 | (comment " |
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| 6 | This file is owned and controlled by Xilinx and must be used |
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| 7 | solely for design, simulation, implementation and creation of |
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| 8 | design files limited to Xilinx devices or technologies. Use |
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| 9 | with non-Xilinx devices or technologies is expressly prohibited |
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| 10 | and immediately terminates your license. |
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| 11 | |
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| 12 | XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS' |
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| 13 | SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR |
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| 14 | XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION |
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| 15 | AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION |
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| 16 | OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS |
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| 17 | IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, |
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| 18 | AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE |
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| 19 | FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY |
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| 20 | WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE |
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| 21 | IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR |
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| 22 | REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF |
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| 23 | INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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| 24 | FOR A PARTICULAR PURPOSE. |
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| 25 | |
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| 26 | Xilinx products are not intended for use in life support |
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| 27 | appliances, devices, or systems. Use in such applications are |
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| 28 | expressly prohibited. |
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| 29 | |
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| 30 | (c) Copyright 1995-2007 Xilinx, Inc. |
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| 31 | All rights reserved. |
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| 32 | |
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| 33 | ") |
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| 34 | (comment "Core parameters: ") |
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| 35 | (comment "c_has_clk = 1 ") |
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| 36 | (comment "c_has_qdpo_clk = 0 ") |
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| 37 | (comment "c_has_qdpo_ce = 0 ") |
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| 38 | (comment "c_has_d = 1 ") |
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| 39 | (comment "c_elaboration_dir = C:\localhome\sgupta\userIOcontroller\netlist01\sysgen\coregen_xp... ") |
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| 40 | (comment " ...yP\coregen_tmp\.\tmp\_cg\ ") |
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| 41 | (comment "c_has_spo = 1 ") |
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| 42 | (comment "c_read_mif = 1 ") |
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| 43 | (comment "c_has_qspo = 0 ") |
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| 44 | (comment "c_width = 1 ") |
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| 45 | (comment "c_reg_a_d_inputs = 0 ") |
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| 46 | (comment "c_has_we = 1 ") |
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| 47 | (comment "c_pipeline_stages = 0 ") |
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| 48 | (comment "c_has_qdpo_rst = 0 ") |
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| 49 | (comment "c_reg_dpra_input = 0 ") |
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| 50 | (comment "c_qualify_we = 0 ") |
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| 51 | (comment "InstanceName = dmg_33_vx4_dcb0c4b6adf24a19 ") |
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| 52 | (comment "c_sync_enable = 1 ") |
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| 53 | (comment "c_depth = 64 ") |
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| 54 | (comment "c_has_qspo_srst = 0 ") |
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| 55 | (comment "c_has_qdpo_srst = 0 ") |
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| 56 | (comment "c_has_dpra = 1 ") |
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| 57 | (comment "c_qce_joined = 0 ") |
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| 58 | (comment "c_mem_type = 2 ") |
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| 59 | (comment "c_has_i_ce = 0 ") |
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| 60 | (comment "c_has_dpo = 1 ") |
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| 61 | (comment "c_mem_init_file = dmg_33_vx4_dcb0c4b6adf24a19.mif ") |
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| 62 | (comment "c_default_data = 0 ") |
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| 63 | (comment "c_has_spra = 0 ") |
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| 64 | (comment "c_has_qspo_ce = 0 ") |
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| 65 | (comment "c_addr_width = 6 ") |
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| 66 | (comment "c_has_qdpo = 0 ") |
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| 67 | (comment "c_has_qspo_rst = 0 ") |
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| 68 | (external xilinxun (edifLevel 0) |
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| 69 | (technology (numberDefinition)) |
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| 70 | (cell VCC (cellType GENERIC) |
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| 71 | (view view_1 (viewType NETLIST) |
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| 72 | (interface |
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| 73 | (port P (direction OUTPUT)) |
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| 74 | ) |
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| 75 | ) |
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| 76 | ) |
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| 77 | (cell GND (cellType GENERIC) |
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| 78 | (view view_1 (viewType NETLIST) |
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| 79 | (interface |
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| 80 | (port G (direction OUTPUT)) |
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| 81 | ) |
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| 82 | ) |
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| 83 | ) |
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| 84 | ) |
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| 85 | (external dmg_33_vx4_dcb0c4b6adf24a19_dist_mem_gen_v3_3_xst_1_lib (edifLevel 0) |
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| 86 | (technology (numberDefinition)) |
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| 87 | (cell dmg_33_vx4_dcb0c4b6adf24a19_dist_mem_gen_v3_3_xst_1 (cellType GENERIC) |
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| 88 | (view view_1 (viewType NETLIST) |
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| 89 | (interface |
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| 90 | (port ( array ( rename a "a(5:0)") 6 ) (direction INPUT)) |
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| 91 | (port ( array ( rename d "d(0:0)") 1 ) (direction INPUT)) |
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| 92 | (port ( array ( rename dpra "dpra(5:0)") 6 ) (direction INPUT)) |
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| 93 | (port ( array ( rename spra "spra(5:0)") 6 ) (direction INPUT)) |
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| 94 | (port clk (direction INPUT)) |
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| 95 | (port we (direction INPUT)) |
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| 96 | (port i_ce (direction INPUT)) |
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| 97 | (port qspo_ce (direction INPUT)) |
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| 98 | (port qdpo_ce (direction INPUT)) |
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| 99 | (port qdpo_clk (direction INPUT)) |
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| 100 | (port qspo_rst (direction INPUT)) |
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| 101 | (port qdpo_rst (direction INPUT)) |
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| 102 | (port qspo_srst (direction INPUT)) |
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| 103 | (port qdpo_srst (direction INPUT)) |
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| 104 | (port ( array ( rename spo "spo(0:0)") 1 ) (direction OUTPUT)) |
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| 105 | (port ( array ( rename dpo "dpo(0:0)") 1 ) (direction OUTPUT)) |
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| 106 | (port ( array ( rename qspo "qspo(0:0)") 1 ) (direction OUTPUT)) |
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| 107 | (port ( array ( rename qdpo "qdpo(0:0)") 1 ) (direction OUTPUT)) |
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| 108 | ) |
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| 109 | ) |
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| 110 | ) |
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| 111 | ) |
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| 112 | (library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time)))) |
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| 113 | (cell dmg_33_vx4_dcb0c4b6adf24a19 |
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| 114 | (cellType GENERIC) (view view_1 (viewType NETLIST) |
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| 115 | (interface |
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| 116 | (port ( array ( rename a "a(5:0)") 6 ) (direction INPUT)) |
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| 117 | (port ( array ( rename d "d(0:0)") 1 ) (direction INPUT)) |
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| 118 | (port ( array ( rename dpra "dpra(5:0)") 6 ) (direction INPUT)) |
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| 119 | (port ( rename clk "clk") (direction INPUT)) |
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| 120 | (port ( rename we "we") (direction INPUT)) |
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| 121 | (port ( array ( rename spo "spo(0:0)") 1 ) (direction OUTPUT)) |
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| 122 | (port ( array ( rename dpo "dpo(0:0)") 1 ) (direction OUTPUT)) |
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| 123 | ) |
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| 124 | (contents |
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| 125 | (instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun)))) |
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| 126 | (instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun)))) |
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| 127 | (instance BU2 |
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| 128 | (viewRef view_1 (cellRef dmg_33_vx4_dcb0c4b6adf24a19_dist_mem_gen_v3_3_xst_1 (libraryRef dmg_33_vx4_dcb0c4b6adf24a19_dist_mem_gen_v3_3_xst_1_lib))) |
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| 129 | ) |
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| 130 | (net N0 |
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| 131 | (joined |
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| 132 | (portRef G (instanceRef GND)) |
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| 133 | (portRef (member spra 0) (instanceRef BU2)) |
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| 134 | (portRef (member spra 1) (instanceRef BU2)) |
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| 135 | (portRef (member spra 2) (instanceRef BU2)) |
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| 136 | (portRef (member spra 3) (instanceRef BU2)) |
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| 137 | (portRef (member spra 4) (instanceRef BU2)) |
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| 138 | (portRef (member spra 5) (instanceRef BU2)) |
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| 139 | (portRef qdpo_clk (instanceRef BU2)) |
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| 140 | (portRef qspo_rst (instanceRef BU2)) |
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| 141 | (portRef qdpo_rst (instanceRef BU2)) |
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| 142 | (portRef qspo_srst (instanceRef BU2)) |
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| 143 | (portRef qdpo_srst (instanceRef BU2)) |
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| 144 | ) |
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| 145 | ) |
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| 146 | (net N1 |
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| 147 | (joined |
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| 148 | (portRef P (instanceRef VCC)) |
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| 149 | (portRef i_ce (instanceRef BU2)) |
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| 150 | (portRef qspo_ce (instanceRef BU2)) |
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| 151 | (portRef qdpo_ce (instanceRef BU2)) |
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| 152 | ) |
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| 153 | ) |
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| 154 | (net (rename N2087 "a(5)") |
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| 155 | (joined |
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| 156 | (portRef (member a 0)) |
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| 157 | (portRef (member a 0) (instanceRef BU2)) |
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| 158 | ) |
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| 159 | ) |
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| 160 | (net (rename N2088 "a(4)") |
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| 161 | (joined |
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| 162 | (portRef (member a 1)) |
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| 163 | (portRef (member a 1) (instanceRef BU2)) |
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| 164 | ) |
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| 165 | ) |
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| 166 | (net (rename N2089 "a(3)") |
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| 167 | (joined |
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| 168 | (portRef (member a 2)) |
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| 169 | (portRef (member a 2) (instanceRef BU2)) |
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| 170 | ) |
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| 171 | ) |
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| 172 | (net (rename N2090 "a(2)") |
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| 173 | (joined |
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| 174 | (portRef (member a 3)) |
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| 175 | (portRef (member a 3) (instanceRef BU2)) |
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| 176 | ) |
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| 177 | ) |
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| 178 | (net (rename N2091 "a(1)") |
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| 179 | (joined |
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| 180 | (portRef (member a 4)) |
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| 181 | (portRef (member a 4) (instanceRef BU2)) |
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| 182 | ) |
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| 183 | ) |
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| 184 | (net (rename N2092 "a(0)") |
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| 185 | (joined |
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| 186 | (portRef (member a 5)) |
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| 187 | (portRef (member a 5) (instanceRef BU2)) |
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| 188 | ) |
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| 189 | ) |
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| 190 | (net (rename N2093 "d(0)") |
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| 191 | (joined |
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| 192 | (portRef (member d 0)) |
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| 193 | (portRef (member d 0) (instanceRef BU2)) |
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| 194 | ) |
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| 195 | ) |
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| 196 | (net (rename N2094 "dpra(5)") |
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| 197 | (joined |
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| 198 | (portRef (member dpra 0)) |
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| 199 | (portRef (member dpra 0) (instanceRef BU2)) |
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| 200 | ) |
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| 201 | ) |
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| 202 | (net (rename N2095 "dpra(4)") |
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| 203 | (joined |
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| 204 | (portRef (member dpra 1)) |
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| 205 | (portRef (member dpra 1) (instanceRef BU2)) |
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| 206 | ) |
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| 207 | ) |
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| 208 | (net (rename N2096 "dpra(3)") |
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| 209 | (joined |
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| 210 | (portRef (member dpra 2)) |
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| 211 | (portRef (member dpra 2) (instanceRef BU2)) |
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| 212 | ) |
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| 213 | ) |
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| 214 | (net (rename N2097 "dpra(2)") |
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| 215 | (joined |
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| 216 | (portRef (member dpra 3)) |
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| 217 | (portRef (member dpra 3) (instanceRef BU2)) |
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| 218 | ) |
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| 219 | ) |
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| 220 | (net (rename N2098 "dpra(1)") |
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| 221 | (joined |
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| 222 | (portRef (member dpra 4)) |
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| 223 | (portRef (member dpra 4) (instanceRef BU2)) |
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| 224 | ) |
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| 225 | ) |
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| 226 | (net (rename N2099 "dpra(0)") |
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| 227 | (joined |
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| 228 | (portRef (member dpra 5)) |
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| 229 | (portRef (member dpra 5) (instanceRef BU2)) |
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| 230 | ) |
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| 231 | ) |
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| 232 | (net (rename N2106 "clk") |
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| 233 | (joined |
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| 234 | (portRef clk) |
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| 235 | (portRef clk (instanceRef BU2)) |
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| 236 | ) |
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| 237 | ) |
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| 238 | (net (rename N2107 "we") |
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| 239 | (joined |
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| 240 | (portRef we) |
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| 241 | (portRef we (instanceRef BU2)) |
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| 242 | ) |
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| 243 | ) |
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| 244 | (net (rename N2116 "spo(0)") |
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| 245 | (joined |
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| 246 | (portRef (member spo 0)) |
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| 247 | (portRef (member spo 0) (instanceRef BU2)) |
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| 248 | ) |
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| 249 | ) |
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| 250 | (net (rename N2117 "dpo(0)") |
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| 251 | (joined |
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| 252 | (portRef (member dpo 0)) |
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| 253 | (portRef (member dpo 0) (instanceRef BU2)) |
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| 254 | ) |
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| 255 | ) |
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| 256 | )))) |
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| 257 | (design dmg_33_vx4_dcb0c4b6adf24a19 (cellRef dmg_33_vx4_dcb0c4b6adf24a19 (libraryRef test_lib)) |
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| 258 | (property X_CORE_INFO (string "dist_mem_gen_v3_3, Xilinx CORE Generator 10.1.03_ip3")) |
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| 259 | (property PART (string "xc4vfx12-sf363-12") (owner "Xilinx")) |
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| 260 | )) |
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