source: PlatformSupport/Deprecated/w3_ad_bridge_v3_00_f/hdl/verilog/w3_ad_bridge.v

/* AD bridge customized for:
    -Externally buffered clocks (0 and 90 degree versions, must match AD9512/AD9963 config)
    -Explicit IDELAYCTRL for designs with no MPMC or TEMACs
    -14-bit user I/Q IO
   Created for testing early OFDM ref designs, before figuring out
    proper timing constraints (to avoid cross-domain errors) and tweaking
    gateways for 12-bit I/Q
*/
module w3_ad_bridge
(
    //Ref clk for IDELAYCTRL
    input clk200,
    
    //BUF'd output for other blocks to use
    input sys_samp_clk,
    input sys_samp_clk_90,
    
    //RF Path A User Ports
    output [0:11] user_RFA_RXD_I,
    output [0:11] user_RFA_RXD_Q,

    input [0:11] user_RFA_TXD_I,
    input [0:11] user_RFA_TXD_Q,

    input user_RFA_TXCLK,
    input user_RFA_TXIQ,

    //RF Path B User Ports
    output [0:11] user_RFB_RXD_I,
    output [0:11] user_RFB_RXD_Q,

    input [0:11] user_RFB_TXD_I,
    input [0:11] user_RFB_TXD_Q,

    input user_RFB_TXCLK,
    input user_RFB_TXIQ,

    //RF Path A AD ports
    output [0:11] ad_RFA_TXD,
    output ad_RFA_TXIQ,
    output ad_RFA_TXCLK,

    input [0:11] ad_RFA_TRXD,
    input ad_RFA_TRXIQ,
    input ad_RFA_TRXCLK,

    //RF Path B AD ports
    output [0:11] ad_RFB_TXD,
    output ad_RFB_TXIQ,
    output ad_RFB_TXCLK,

    input [0:11] ad_RFB_TRXD,
    input ad_RFB_TRXIQ,
    input ad_RFB_TRXCLK
);

parameter C_FAMILY = "virtex6";
parameter INCLUDE_IDELAYCTRL = 1;

wire user_RFA_TXCLK_ddr, user_RFB_TXCLK_ddr;

assign ad_RFA_TXIQ = user_RFA_TXIQ;
assign ad_RFB_TXIQ = user_RFB_TXIQ;

generate
if(INCLUDE_IDELAYCTRL==1) begin
IDELAYCTRL IDELAYCTRL_inst (
      .RDY(),       // 1-bit Ready output
      .REFCLK(clk200), // 1-bit Reference clock input
      .RST(1'b0)        // 1-bit Reset input
   );
end
endgenerate

//Use DDR primitives for cleanest output clock
ODDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
    .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
    .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
) OBUFDDR_RFA_TXCLK (
    .Q(ad_RFA_TXCLK),   // 1-bit DDR output
    .C(sys_samp_clk_90),   // 1-bit clock input
    .CE(1'b1), // 1-bit clock enable input
    .D1(1'b1), // 1-bit data input (positive edge)
    .D2(1'b0), // 1-bit data input (negative edge)
    .R(1'b0),   // 1-bit reset
    .S(1'b0)    // 1-bit set
);

ODDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
    .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
    .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
) OBUFDDR_RFB_TXCLK (
    .Q(ad_RFB_TXCLK),   // 1-bit DDR output
    .C(sys_samp_clk_90),   // 1-bit clock input
    .CE(1'b1), // 1-bit clock enable input
    .D1(1'b1), // 1-bit data input (positive edge)
    .D2(1'b0), // 1-bit data input (negative edge)
    .R(1'b0),   // 1-bit reset
    .S(1'b0)    // 1-bit set
);


wire ad_RFA_TRXCLK_buf, ad_RFB_TRXCLK_buf;
wire ad_RFA_TRXCLK_dly, ad_RFB_TRXCLK_dly;

//Delay AD9963-generated TRXCLK, then drive BUFIO for latching TRXD DDR inputs
IODELAYE1 #(
    .CINVCTRL_SEL("FALSE"),          // Enable dynamic clock inversion ("TRUE"/"FALSE") 
    .DELAY_SRC("I"),                 // Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
    .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
    .IDELAY_TYPE("FIXED"),           // "FIXED", "VARIABLE", or "VAR_LOADABLE" 
    .IDELAY_VALUE(31),                // Output delay tap setting (0-32)
    .REFCLK_FREQUENCY(200.0),        // IDELAYCTRL clock input frequency in MHz
    .SIGNAL_PATTERN("CLOCK")          // "DATA" or "CLOCK" input signal
) IDELAY_RFA_TRXCLK (
    .IDATAIN(ad_RFA_TRXCLK),
    .DATAOUT(ad_RFA_TRXCLK_dly),
    .T(1'b0)                      // 1-bit input - 3-state input control. Tie high for input-only or internal delay or
);

IODELAYE1 #(
    .CINVCTRL_SEL("FALSE"),          // Enable dynamic clock inversion ("TRUE"/"FALSE") 
    .DELAY_SRC("I"),                 // Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
    .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
    .IDELAY_TYPE("FIXED"),           // "FIXED", "VARIABLE", or "VAR_LOADABLE" 
    .IDELAY_VALUE(31),                // Output delay tap setting (0-32)
    .REFCLK_FREQUENCY(200.0),        // IDELAYCTRL clock input frequency in MHz
    .SIGNAL_PATTERN("CLOCK")          // "DATA" or "CLOCK" input signal
) IDELAY_RFB_TRXCLK (
    .IDATAIN(ad_RFB_TRXCLK),
    .DATAOUT(ad_RFB_TRXCLK_dly),
    .T(1'b0)                      // 1-bit input - 3-state input control. Tie high for input-only or internal delay or
);

BUFIO BUFIO_RFA_TRXCLK (
    .O(ad_RFA_TRXCLK_buf),     // Clock buffer output
    .I(ad_RFA_TRXCLK_dly)      // Clock buffer input
);

BUFIO BUFIO_RFB_TRXCLK (
    .O(ad_RFB_TRXCLK_buf),     // Clock buffer output
    .I(ad_RFB_TRXCLK_dly)      // Clock buffer input
);

wire [0:11] user_RFA_RXD_I_src;
wire [0:11] user_RFA_RXD_Q_src;
wire [0:11] user_RFB_RXD_I_src;
wire [0:11] user_RFB_RXD_Q_src;

//Instantiate all the DDR registers for TXD and TRXD I/O
// Only selects bits [0:11] (12MSB) of 14-bit Tx I/Q samples provided by user logic
genvar ii;
generate
    for(ii=0; ii<12; ii=ii+1) begin: DDR_REGS_RFA_RFB
        ODDR #(
            .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
            .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
            .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
        ) ODDR_RFA_TXD (
            .Q(ad_RFA_TXD[ii]),   // 1-bit DDR output
            .C(sys_samp_clk),   // 1-bit clock input
            .CE(1'b1), // 1-bit clock enable input
            .D1(user_RFA_TXD_I[ii]), // 1-bit data input (positive edge)
            .D2(user_RFA_TXD_Q[ii]), // 1-bit data input (negative edge)
            .R(1'b0),   // 1-bit reset
            .S(1'b0)    // 1-bit set
        );
        ODDR #(
            .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
            .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
            .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
        ) ODDR_RFB_TXD (
            .Q(ad_RFB_TXD[ii]),   // 1-bit DDR output
            .C(sys_samp_clk),   // 1-bit clock input
            .CE(1'b1), // 1-bit clock enable input
            .D1(user_RFB_TXD_I[ii]), // 1-bit data input (positive edge)
            .D2(user_RFB_TXD_Q[ii]), // 1-bit data input (negative edge)
            .R(1'b0),   // 1-bit reset
            .S(1'b0)    // 1-bit set
        );


        IDDR #(
            .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" 
            .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
            .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
            .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
        ) IDDR_RFA_TRXD (
            .Q1(user_RFA_RXD_I_src[ii]), // 1-bit output for positive edge of clock 
            .Q2(user_RFA_RXD_Q_src[ii]), // 1-bit output for negative edge of clock
            .C(ad_RFA_TRXCLK_buf),   // 1-bit clock input
            .CE(1'b1), // 1-bit clock enable input
            .D(ad_RFA_TRXD[ii]),   // 1-bit DDR data input
            .R(1'b0),   // 1-bit reset
            .S(1'b0)    // 1-bit set
        );
        IDDR #(
            .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" 
            .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
            .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
            .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
        ) IDDR_RFB_TRXD (
            .Q1(user_RFB_RXD_I_src[ii]), // 1-bit output for positive edge of clock 
            .Q2(user_RFB_RXD_Q_src[ii]), // 1-bit output for negative edge of clock
            .C(ad_RFB_TRXCLK_buf),   // 1-bit clock input
            .CE(1'b1), // 1-bit clock enable input
            .D(ad_RFB_TRXD[ii]),   // 1-bit DDR data input
            .R(1'b0),   // 1-bit reset
            .S(1'b0)    // 1-bit set
        );
        
        //D flip flops to connect source-syncronous inputs to samp_clk domain (TRXCLK and samp_clk have same rate, arbitrary phases)
        FDSE #(.INIT(1'b0)) DFF2_RFA_I (.D(user_RFA_RXD_I_src[ii]), .Q(user_RFA_RXD_I[ii]), .C(sys_samp_clk), .S(1'b0), .CE(1'b1));
        FDSE #(.INIT(1'b0)) DFF2_RFA_Q (.D(user_RFA_RXD_Q_src[ii]), .Q(user_RFA_RXD_Q[ii]), .C(sys_samp_clk), .S(1'b0), .CE(1'b1));
        FDSE #(.INIT(1'b0)) DFF2_RFB_I (.D(user_RFB_RXD_I_src[ii]), .Q(user_RFB_RXD_I[ii]), .C(sys_samp_clk), .S(1'b0), .CE(1'b1));
        FDSE #(.INIT(1'b0)) DFF2_RFB_Q (.D(user_RFB_RXD_Q_src[ii]), .Q(user_RFB_RXD_Q[ii]), .C(sys_samp_clk), .S(1'b0), .CE(1'b1));
        end
endgenerate

endmodule