source: PlatformSupport/XBD/boards/Rice_University_WARP_FPGA_V2P70/data/Rice_University_WARP_FPGA_V2P70_v2_2_0.xbd

Last change on this file was 1058, checked in by murphpo, 16 years ago
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1# -------------------------------------------------------------
2#  Copyright (c) 2006 Rice University
3#  All Rights Reserved
4#  This code is covered by the Rice-WARP license
5#  See http://warp.rice.edu/license/ for details
6# -------------------------------------------------------------
7
8# Define the attributes of the board that will be displayed when listing the board.
9ATTRIBUTE VENDOR = Rice University - WARP Project
10ATTRIBUTE SPEC_URL = http://warp.rice.edu/
11ATTRIBUTE CONTACT_INFO_URL= http://warp.rice.edu/
12ATTRIBUTE NAME = WARP FPGA Board
13ATTRIBUTE REVISION = FPGA 1.2
14ATTRIBUTE DESC = Rice University WARP
15ATTRIBUTE LONG_DESC = 'This board utilizes a Xilinx Virtex-II Pro FPGA XC2VP70-FF1517-6C. This XBD enables: 4 LEDs, 2 Hex Displays, 1 Reset Button, 4 Push-Buttons, SystemACE CompactFlash MCU interface, UART, 2 512kx32b ZBT SRAMs, Ethernet & OneWire EEPROM. It configures the XPS clock_generator to be driven by the 100MHz oscillator on the FPGA board. This XBD does not support use of the WARP clock and radio boards.'
16# Defining hardware interfaces
17
18# Define the first clock which is the processor clock. IOTYPE = XIL_CLOCK_V1 defines a general clock.
19# port name can be named as desired but remain consistent when defining the pins in the FPGA section.
20BEGIN IO_INTERFACE
21    ATTRIBUTE IOTYPE = XIL_CLOCK_V1
22    ATTRIBUTE INSTANCE =GCLK0
23    PARAMETER CLK_FREQ =100000000, IO_IS=clk_freq, RANGE=(100000000) # 100 MHz
24    PORT GCLK5S = CONN_GCLK0_GCLK5S , IO_IS=ext_clk
25END
26
27# Defines the reset interface.  Currently set to use first push button
28BEGIN IO_INTERFACE
29    ATTRIBUTE IOTYPE = XIL_RESET_V1
30    ATTRIBUTE INSTANCE = rst_0
31    PARAMETER RST_POLARITY =1, IO_IS=polarity, VALUE_NOTE=Active HIGH
32    PORT INIT =  CONN_INIT_INIT, IO_IS=ext_rst
33END
34
35# A single GPIO core is used to interface with:
36#  4 user LEDs (4-bits)
37#  2 7-segment displays (14-bits)
38#  4 push buttons (4-bits)
39#  DIP switch (4-bits)
40BEGIN IO_INTERFACE
41    ATTRIBUTE IOTYPE = XIL_GPIO_V1
42    ATTRIBUTE INSTANCE = USER_IO
43    PARAMETER num_bits = 18, IO_IS=num_bits
44    PARAMETER is_dual=1, IO_IS=is_dual          # Single channel
45    PARAMETER bidir_data = 0, IO_IS=is_bidir    # No bi-directional I/O
46    PARAMETER all_inputs = 1, IO_IS=all_inputs  # Channel 1 is all inputs
47    PARAMETER bidir_data_2 = 1, IO_IS=is_bidir_2    #
48    PARAMETER all_inputs_2 = 0, IO_IS=all_inputs_2  # Channel 2 is all outputs
49
50    #Channel 1 - User Inputs (buttons and switches)
51    PORT SW_0 = SW_0, IO_IS = gpio_data_in[0]
52    PORT SW_1 = SW_1, IO_IS = gpio_data_in[1]
53    PORT SW_2 = SW_2, IO_IS = gpio_data_in[2]
54    PORT SW_3 = SW_3, IO_IS = gpio_data_in[3]
55
56    PORT PUSHU = CONN_PUSHU, IO_IS = gpio_data_in[4]
57    PORT PUSHL = CONN_PUSHL, IO_IS = gpio_data_in[5]
58    PORT PUSHR = CONN_PUSHR, IO_IS = gpio_data_in[6]
59    PORT PUSHC = CONN_PUSHC, IO_IS = gpio_data_in[7]
60
61    #Channel 2 - User Outputs (LEDs and hex displays)
62    PORT SEG_LED0 = CONN_0_SEG1, IO_IS = gpio_data_out_2[0]
63    PORT SEG_LED1 = CONN_0_SEG2, IO_IS = gpio_data_out_2[1]
64    PORT SEG_LED2 = CONN_0_SEG3, IO_IS = gpio_data_out_2[2]
65    PORT SEG_LED3 = CONN_0_SEG4, IO_IS = gpio_data_out_2[3]
66    PORT SEG_LED4 = CONN_0_SEG5, IO_IS = gpio_data_out_2[4]
67    PORT SEG_LED5 = CONN_0_SEG6, IO_IS = gpio_data_out_2[5]
68    PORT SEG_LED6 = CONN_0_SEG7, IO_IS = gpio_data_out_2[6]
69
70    PORT SEG_1_LED0 = CONN_1_SEG1, IO_IS = gpio_data_out_2[7]
71    PORT SEG_1_LED1 = CONN_1_SEG2, IO_IS = gpio_data_out_2[8]
72    PORT SEG_1_LED2 = CONN_1_SEG3, IO_IS = gpio_data_out_2[9]
73    PORT SEG_1_LED3 = CONN_1_SEG4, IO_IS = gpio_data_out_2[10]
74    PORT SEG_1_LED4 = CONN_1_SEG5, IO_IS = gpio_data_out_2[11]
75    PORT SEG_1_LED5 = CONN_1_SEG6, IO_IS = gpio_data_out_2[12]
76    PORT SEG_1_LED6 = CONN_1_SEG7, IO_IS = gpio_data_out_2[13]
77   
78    PORT LED0 = CONN_LEDs_LED0, IO_IS = gpio_data_out_2[14]
79    PORT LED1 = CONN_LEDs_LED1, IO_IS = gpio_data_out_2[15]
80    PORT LED2 = CONN_LEDs_LED2, IO_IS = gpio_data_out_2[16]
81    PORT LED3 = CONN_LEDs_LED3, IO_IS = gpio_data_out_2[17]
82END       
83
84# This is the serial port.
85BEGIN IO_INTERFACE
86    ATTRIBUTE IOTYPE = XIL_UART_V1
87    ATTRIBUTE INSTANCE = rs232
88    PORT RXD = CONN_RXD, IO_IS=serial_in
89    PORT TXD = CONN_TXD, IO_IS=serial_out
90END       
91
92# SystemACE Compact Flash microprocessor interface
93BEGIN IO_INTERFACE
94    ATTRIBUTE IOTYPE = XIL_SYSACE_V1
95    ATTRIBUTE INSTANCE = sysace_compactflash
96    PARAMETER C_MEM_WIDTH =16, IO_IS=mem_data_bus_width 
97    PORT X104_5_OUT = sysace_clk, IO_IS=clk_in
98    PORT X104_1_OE = sysace_clk_oe_n, IO_IS=clk_enable_n, INITIALVAL = VCC
99    PORT MPA00 = sysace_mpa_0, IO_IS = address[0]
100    PORT MPA01 = sysace_mpa_1, IO_IS = address[1]
101    PORT MPA02 = sysace_mpa_2, IO_IS = address[2]
102    PORT MPA03 = sysace_mpa_3, IO_IS = address[3]
103    PORT MPA04 = sysace_mpa_4, IO_IS = address[4]
104    PORT MPA05 = sysace_mpa_5, IO_IS = address[5]
105    PORT MPA06 = sysace_mpa_6, IO_IS = address[6]
106    PORT MPD00 = sysace_mpd_0, IO_IS = data[0]   
107    PORT MPD01 = sysace_mpd_1, IO_IS = data[1]   
108    PORT MPD02 = sysace_mpd_2, IO_IS = data[2]   
109    PORT MPD03 = sysace_mpd_3, IO_IS = data[3]   
110    PORT MPD04 = sysace_mpd_4, IO_IS = data[4]   
111    PORT MPD05 = sysace_mpd_5, IO_IS = data[5]   
112    PORT MPD06 = sysace_mpd_6, IO_IS = data[6]   
113    PORT MPD07 = sysace_mpd_7, IO_IS = data[7]
114    PORT MPD08 = sysace_mpd_8, IO_IS = data[8]
115    PORT MPD09 = sysace_mpd_9, IO_IS = data[9]
116    PORT MPD10 = sysace_mpd_10, IO_IS = data[10]
117    PORT MPD11 = sysace_mpd_11, IO_IS = data[11]
118    PORT MPD12 = sysace_mpd_12, IO_IS = data[12]
119    PORT MPD13 = sysace_mpd_13, IO_IS = data[13]
120    PORT MPD14 = sysace_mpd_14, IO_IS = data[14]
121    PORT MPD15 = sysace_mpd_15, IO_IS = data[15]
122    PORT MPCE  = sysace_mpce, IO_IS=chip_enable 
123    PORT MPOE  = sysace_mpoe, IO_IS=output_enable
124    PORT MPWE  = sysace_mpwe, IO_IS=write_enable
125    PORT MPIRQ = sysace_mpirq, IO_IS=intr_out     
126END
127
128# EEPROM Serial Number and Memory interface
129BEGIN IO_INTERFACE
130    ATTRIBUTE IOTYPE = WARP_EEPROM_V1
131    ATTRIBUTE INSTANCE = eeprom_controller
132    PORT DQ0   = EEPROM_0_DQ0, INITIALVAL = VCC
133#   PORT DQ0_T =
134#   PORT DQ0_O =
135#   PORT DQ0_I =
136
137#   PORT DQ1   =
138    PORT DQ1_T = DQ1_T_user_EEPROM_IO_T
139    PORT DQ1_O = DQ1_O_user_EEPROM_IO_O
140    PORT DQ1_I = DQ1_I_user_EEPROM_IO_I, INITIALVAL = VCC
141
142#   PORT DQ2   =
143    PORT DQ2_T = DQ2_T_user_EEPROM_IO_T
144    PORT DQ2_O = DQ2_O_user_EEPROM_IO_O
145    PORT DQ2_I = DQ2_I_user_EEPROM_IO_I, INITIALVAL = VCC
146
147#   PORT DQ3   =
148    PORT DQ3_T = DQ3_T_user_EEPROM_IO_T
149    PORT DQ3_O = DQ3_O_user_EEPROM_IO_O
150    PORT DQ3_I = DQ3_I_user_EEPROM_IO_I, INITIALVAL = VCC
151
152#   PORT DQ4   =
153    PORT DQ4_T = DQ4_T_user_EEPROM_IO_T
154    PORT DQ4_O = DQ4_O_user_EEPROM_IO_O
155    PORT DQ4_I = DQ4_I_user_EEPROM_IO_I, INITIALVAL = VCC
156
157#   PORT DQ5   =
158#   PORT DQ5_T =
159#   PORT DQ5_O =
160    PORT DQ5_I = "net_vcc"
161
162#   PORT DQ6   =
163#   PORT DQ6_T =
164#   PORT DQ6_O =
165    PORT DQ6_I = "net_vcc"
166
167#   PORT DQ7   =
168#   PORT DQ7_T =
169#   PORT DQ7_O =
170    PORT DQ7_I = "net_vcc"
171END
172
173# LTX972A Ethernet MAC (10/100)
174BEGIN IO_INTERFACE
175    ATTRIBUTE IOTYPE = XIL_ETHERNET_V1
176    ATTRIBUTE INSTANCE = Ethernet_MAC
177    PORT TXSLEW0  = phy_slew0, IO_IS=slew1,      INITIALVAL = VCC
178    PORT TXSLEW1  = phy_slew1, IO_IS=slew2,      INITIALVAL = VCC
179    PORT RESET    = phy_rst_n, IO_IS=PHY_RESETn, INITIALVAL = VCC
180    PORT MDINT    = phy_mii_int_n, IO_IS = mii_int_n
181    PORT CRS      = phy_crs,       IO_IS = ETH_CRS
182    PORT COL      = phy_col,       IO_IS = ETH_COL
183    PORT TXD3     = phy_tx_data_3, IO_IS = ETH_TXD[3]
184    PORT TXD2     = phy_tx_data_2, IO_IS = ETH_TXD[2]
185    PORT TXD1     = phy_tx_data_1, IO_IS = ETH_TXD[1]
186    PORT TXD0     = phy_tx_data_0, IO_IS = ETH_TXD[0]
187    PORT TX_EN    = phy_tx_en,     IO_IS = ETH_TXEN
188    PORT TX_CLK   = phy_tx_clk,    IO_IS = ETH_TXC
189    PORT TX_ER    = phy_tx_er,     IO_IS = ETH_TXER
190    PORT RX_ER    = phy_rx_er,     IO_IS = ETH_RXER
191    PORT RX_CLK   = phy_rx_clk,    IO_IS = ETH_RXC
192    PORT RX_DV    = phy_dv,        IO_IS = ETH_RXDV
193    PORT RXD0     = phy_rx_data_0, IO_IS = ETH_RXD[0]
194    PORT RXD1     = phy_rx_data_1, IO_IS = ETH_RXD[1]
195    PORT RXD2     = phy_rx_data_2, IO_IS = ETH_RXD[2]
196    PORT RXD3     = phy_rx_data_3, IO_IS = ETH_RXD[3]
197    PORT PHY_MDC  = phy_mii_clk,   IO_IS = ETH_MDC
198    PORT PHY_MDIO = phy_mii_data,  IO_IS = ETH_MDIO
199END
200
201
202# One user I/O board controller handles a single board
203#  The user can enabled up to four controllers (one per slot)
204BEGIN IO_INTERFACE
205    ATTRIBUTE IOTYPE = XIL_USERIOBOARD_V1
206    ATTRIBUTE INSTANCE = user_io_board_controller_slot1
207    ATTRIBUTE EXCLUSIVE = slot1
208
209    #Hardware reset input (same as software reset)
210    PORT reset = userio_board_slot1_reset, IO_IS = userio_board_reset
211
212    #LCD SPI interface
213    PORT sdi = user_ioboard_slot1_sdi, IO_IS = userio_board_sdi
214    PORT scl = userio_board_slot1_scl, IO_IS = userio_board_scl
215    PORT resetlcd = userio_board_slot1_resetlcd, IO_IS = userio_board_resetlcd
216    PORT cs = userio_board_slot1_cs, IO_IS = userio_board_cs
217
218    #Buzzer output
219    PORT buzzer = userio_board_slot1_buzzer, IO_IS = userio_board_buzzer
220
221    #Trackball I/O
222    PORT trackball_yscn = userio_board_slot1_trackball_yscn, IO_IS = userio_board_trackball_yscn
223    PORT trackball_sel1 = userio_board_slot1_trackball_sel1, IO_IS = userio_board_trackball_sel1
224    PORT trackball_xscn = userio_board_slot1_trackball_xscn, IO_IS = userio_board_trackball_xscn
225    PORT trackball_sel2 = userio_board_slot1_trackball_sel2, IO_IS = userio_board_trackball_sel2
226    PORT trackball_oyn = userio_board_slot1_trackball_oyn, IO_IS = userio_board_trackball_oyn
227    PORT trackball_oy = userio_board_slot1_trackball_oy, IO_IS = userio_board_trackball_oy
228    PORT trackball_oxn = userio_board_slot1_trackball_oxn, IO_IS = userio_board_trackball_oxn
229    PORT trackball_ox = userio_board_slot1_trackball_ox, IO_IS = userio_board_trackball_ox
230
231    #Eight LEDs
232    PORT leds_0 = userio_board_slot1_leds_0, IO_IS = userio_board_leds[0]
233    PORT leds_1 = userio_board_slot1_leds_1, IO_IS = userio_board_leds[1]
234    PORT leds_2 = userio_board_slot1_leds_2, IO_IS = userio_board_leds[2]
235    PORT leds_3 = userio_board_slot1_leds_3, IO_IS = userio_board_leds[3]
236    PORT leds_4 = userio_board_slot1_leds_4, IO_IS = userio_board_leds[4]
237    PORT leds_5 = userio_board_slot1_leds_5, IO_IS = userio_board_leds[5]
238    PORT leds_6 = userio_board_slot1_leds_6, IO_IS = userio_board_leds[6]
239    PORT leds_7 = userio_board_slot1_leds_7, IO_IS = userio_board_leds[7]
240
241    #DIP switch
242    PORT dip_switch_0 = userio_board_slot1_dip_switch_0, IO_IS = userio_board_dip_switch[0]
243    PORT dip_switch_1 = userio_board_slot1_dip_switch_1, IO_IS = userio_board_dip_switch[1]
244    PORT dip_switch_2 = userio_board_slot1_dip_switch_2, IO_IS = userio_board_dip_switch[2]
245    PORT dip_switch_3 = userio_board_slot1_dip_switch_3, IO_IS = userio_board_dip_switch[3]
246
247    #Six small push buttons
248    PORT buttons_small_0 = userio_board_slot1_buttons_small_0, IO_IS = userio_board_buttons_small[0]
249    PORT buttons_small_1 = userio_board_slot1_buttons_small_1, IO_IS = userio_board_buttons_small[1]
250    PORT buttons_small_2 = userio_board_slot1_buttons_small_2, IO_IS = userio_board_buttons_small[2]
251    PORT buttons_small_3 = userio_board_slot1_buttons_small_3, IO_IS = userio_board_buttons_small[3]
252    PORT buttons_small_4 = userio_board_slot1_buttons_small_4, IO_IS = userio_board_buttons_small[4]
253    PORT buttons_small_5 = userio_board_slot1_buttons_small_5, IO_IS = userio_board_buttons_small[5]
254
255    #Two big push buttons
256    PORT buttons_big_0 = userio_board_slot1_buttons_big_0, IO_IS = userio_board_buttons_big[0]
257    PORT buttons_big_1 = userio_board_slot1_buttons_big_1, IO_IS = userio_board_buttons_big[1]
258END
259
260BEGIN IO_INTERFACE
261    ATTRIBUTE IOTYPE = XIL_EMC_V1
262    ATTRIBUTE INSTANCE = SRAM0_ZBT_512Kx32
263    PARAMETER C_NUM_BANKS_MEM = 1, IO_IS=C_NUM_BANKS_MEM
264    PARAMETER C_DEV_MIR_ENABLE = 0, IO_IS=C_DEV_MIR_ENABLE
265    PARAMETER C_MAX_MEM_WIDTH = 32, IO_IS=C_MAX_MEM_WIDTH
266    PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1, IO_IS=C_INCLUDE_NEGEDGE_IOREGS
267
268    PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1, IO_IS=C_INCLUDE_BURST_CACHELN_SUPPORT
269    PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1, IO_IS=C_INCLUDE_DATAWIDTH_MATCHING_0
270    PARAMETER C_MEM0_BASEADDR = 0x0, IO_IS=C_MEM0_BASEADDR, SHORT_DESC=SRAM_256Kx32
271    PARAMETER C_MEM0_HIGHADDR = 0x1FFFFF, IO_IS=C_MEM0_HIGHADDR
272    PARAMETER C_MEM0_WIDTH = 32, IO_IS=C_MEM0_WIDTH
273    PARAMETER C_SYNCH_MEM_0 = 1, IO_IS=C_SYNCH_MEM_0
274    PARAMETER C_SYNCH_PIPEDELAY_0 = 2, IO_IS=C_SYNCH_PIPEDELAY_0
275
276    PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 0,  IO_IS = C_READ_ADDR_TO_OUT_SLOW_PS_0
277    PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 0, IO_IS = C_WRITE_ADDR_TO_OUT_SLOW_PS_0
278    PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 0,  IO_IS = C_WRITE_MIN_PULSE_WIDTH_PS_0
279    PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 0,  IO_IS = C_READ_ADDR_TO_OUT_FAST_PS_0
280    PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 0, IO_IS = C_WRITE_ADDR_TO_OUT_FAST_PS_0
281    PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 0, IO_IS = C_READ_RECOVERY_BEFORE_WRITE_PS_0
282    PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 0, IO_IS = C_WRITE_RECOVERY_BEFORE_READ_PS_0
283
284    PORT A0 = CONN_SRAM0_A0, IO_IS = emc_addr[29]
285    PORT A1 = CONN_SRAM0_A1, IO_IS = emc_addr[28]
286    PORT A2 = CONN_SRAM0_A2, IO_IS = emc_addr[27]
287    PORT A3 = CONN_SRAM0_A3, IO_IS = emc_addr[26]
288    PORT A4 = CONN_SRAM0_A4, IO_IS = emc_addr[25]
289    PORT A5 = CONN_SRAM0_A5, IO_IS = emc_addr[24]
290    PORT A6 = CONN_SRAM0_A6, IO_IS = emc_addr[23]
291    PORT A7 = CONN_SRAM0_A7, IO_IS = emc_addr[22]
292    PORT A8 = CONN_SRAM0_A8, IO_IS = emc_addr[21]
293    PORT A9 = CONN_SRAM0_A9, IO_IS = emc_addr[20]
294    PORT A10 = CONN_SRAM0_A10, IO_IS = emc_addr[19]
295    PORT A11 = CONN_SRAM0_A11, IO_IS = emc_addr[18]
296    PORT A12 = CONN_SRAM0_A12, IO_IS = emc_addr[17]
297    PORT A13 = CONN_SRAM0_A13, IO_IS = emc_addr[16]
298    PORT A14 = CONN_SRAM0_A14, IO_IS = emc_addr[15]
299    PORT A15 = CONN_SRAM0_A15, IO_IS = emc_addr[14]
300    PORT A16 = CONN_SRAM0_A16, IO_IS = emc_addr[13]
301    PORT A17 = CONN_SRAM0_A17, IO_IS = emc_addr[12]
302    PORT A18 = CONN_SRAM0_A18, IO_IS = emc_addr[11]
303
304    PORT BEN0 = CONN_SRAM0_BEN0, IO_IS = emc_ben[3]
305    PORT BEN1 = CONN_SRAM0_BEN1, IO_IS = emc_ben[2]
306    PORT BEN2 = CONN_SRAM0_BEN2, IO_IS = emc_ben[1]
307    PORT BEN3 = CONN_SRAM0_BEN3, IO_IS = emc_ben[0]
308    PORT WEN = CONN_SRAM0_WEN, IO_IS=emc_wen
309
310    PORT D0 = CONN_SRAM0_D0, IO_IS = emc_data[31]
311    PORT D1 = CONN_SRAM0_D1, IO_IS = emc_data[30]
312    PORT D2 = CONN_SRAM0_D2, IO_IS = emc_data[29]
313    PORT D3 = CONN_SRAM0_D3, IO_IS = emc_data[28]
314    PORT D4 = CONN_SRAM0_D4, IO_IS = emc_data[27]
315    PORT D5 = CONN_SRAM0_D5, IO_IS = emc_data[26]
316    PORT D6 = CONN_SRAM0_D6,  IO_IS = emc_data[25]
317    PORT D7 = CONN_SRAM0_D7, IO_IS = emc_data[24]
318    PORT D8 = CONN_SRAM0_D8, IO_IS = emc_data[23]
319    PORT D9 = CONN_SRAM0_D9, IO_IS = emc_data[22]
320    PORT D10 = CONN_SRAM0_D10, IO_IS = emc_data[21]
321    PORT D11 = CONN_SRAM0_D11, IO_IS = emc_data[20]
322    PORT D12 = CONN_SRAM0_D12, IO_IS = emc_data[19]
323    PORT D13 = CONN_SRAM0_D13, IO_IS = emc_data[18]
324    PORT D14 = CONN_SRAM0_D14, IO_IS = emc_data[17]
325    PORT D15 = CONN_SRAM0_D15, IO_IS = emc_data[16]
326    PORT D16 = CONN_SRAM0_D16, IO_IS = emc_data[15]
327    PORT D17 = CONN_SRAM0_D17, IO_IS = emc_data[14]
328    PORT D18 = CONN_SRAM0_D18, IO_IS = emc_data[13]
329    PORT D19 = CONN_SRAM0_D19, IO_IS = emc_data[12]
330    PORT D20 = CONN_SRAM0_D20, IO_IS = emc_data[11]
331    PORT D21 = CONN_SRAM0_D21, IO_IS = emc_data[10]
332    PORT D22 = CONN_SRAM0_D22, IO_IS = emc_data[9]
333    PORT D23 = CONN_SRAM0_D23, IO_IS = emc_data[8]
334    PORT D24 = CONN_SRAM0_D24, IO_IS = emc_data[7]
335    PORT D25 = CONN_SRAM0_D25, IO_IS = emc_data[6]
336    PORT D26 = CONN_SRAM0_D26, IO_IS = emc_data[5]
337    PORT D27 = CONN_SRAM0_D27, IO_IS = emc_data[4]
338    PORT D28 = CONN_SRAM0_D28, IO_IS = emc_data[3]
339    PORT D29 = CONN_SRAM0_D29, IO_IS = emc_data[2]
340    PORT D30 = CONN_SRAM0_D30, IO_IS = emc_data[1]
341    PORT D31 = CONN_SRAM0_D31, IO_IS = emc_data[0]
342
343    PORT OEN = CONN_SRAM0_OEN, IO_IS = emc_oen[0]
344    PORT ADV_LDN = CONN_SRAM0_ADV_LDN, IO_IS = emc_adv_ldn
345    PORT ZBT_CLK_OUT = CONN_SRAM0_CLK, IO_IS=EMC_CLK_OUT
346
347    PORT CKEN_PORT = CONN_SRAM0_CKEN, IO_IS = emc_cken
348    PORT CE_PORT = CONN_SRAM0_CE, IO_IS = emc_ce   
349END
350
351BEGIN IO_INTERFACE
352    ATTRIBUTE IOTYPE = XIL_EMC_V1
353    ATTRIBUTE INSTANCE = SRAM1_ZBT_512Kx32
354    PARAMETER C_NUM_BANKS_MEM = 1, IO_IS=C_NUM_BANKS_MEM
355    PARAMETER C_DEV_MIR_ENABLE = 0, IO_IS=C_DEV_MIR_ENABLE
356    PARAMETER C_MAX_MEM_WIDTH = 32, IO_IS=C_MAX_MEM_WIDTH
357    PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1, IO_IS=C_INCLUDE_NEGEDGE_IOREGS
358
359    PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1, IO_IS=C_INCLUDE_BURST_CACHELN_SUPPORT
360    PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1, IO_IS=C_INCLUDE_DATAWIDTH_MATCHING_0
361    PARAMETER C_MEM0_BASEADDR = 0x0, IO_IS=C_MEM0_BASEADDR, SHORT_DESC=SRAM_256Kx32
362    PARAMETER C_MEM0_HIGHADDR = 0x1FFFFF, IO_IS=C_MEM0_HIGHADDR
363    PARAMETER C_MEM0_WIDTH = 32, IO_IS=C_MEM0_WIDTH
364    PARAMETER C_SYNCH_MEM_0 = 1, IO_IS=C_SYNCH_MEM_0
365    PARAMETER C_SYNCH_PIPEDELAY_0 = 2, IO_IS=C_SYNCH_PIPEDELAY_0
366
367    PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 0,  IO_IS = C_READ_ADDR_TO_OUT_SLOW_PS_0
368    PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 0, IO_IS = C_WRITE_ADDR_TO_OUT_SLOW_PS_0
369    PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 0,  IO_IS = C_WRITE_MIN_PULSE_WIDTH_PS_0
370    PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 0,  IO_IS = C_READ_ADDR_TO_OUT_FAST_PS_0
371    PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 0, IO_IS = C_WRITE_ADDR_TO_OUT_FAST_PS_0
372    PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 0, IO_IS = C_READ_RECOVERY_BEFORE_WRITE_PS_0
373    PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 0, IO_IS = C_WRITE_RECOVERY_BEFORE_READ_PS_0
374
375    PORT A0 = CONN_SRAM1_A0, IO_IS = emc_addr[29]
376    PORT A1 = CONN_SRAM1_A1, IO_IS = emc_addr[28]
377    PORT A2 = CONN_SRAM1_A2, IO_IS = emc_addr[27]
378    PORT A3 = CONN_SRAM1_A3, IO_IS = emc_addr[26]
379    PORT A4 = CONN_SRAM1_A4, IO_IS = emc_addr[25]
380    PORT A5 = CONN_SRAM1_A5, IO_IS = emc_addr[24]
381    PORT A6 = CONN_SRAM1_A6, IO_IS = emc_addr[23]
382    PORT A7 = CONN_SRAM1_A7, IO_IS = emc_addr[22]
383    PORT A8 = CONN_SRAM1_A8, IO_IS = emc_addr[21]
384    PORT A9 = CONN_SRAM1_A9, IO_IS = emc_addr[20]
385    PORT A10 = CONN_SRAM1_A10, IO_IS = emc_addr[19]
386    PORT A11 = CONN_SRAM1_A11, IO_IS = emc_addr[18]
387    PORT A12 = CONN_SRAM1_A12, IO_IS = emc_addr[17]
388    PORT A13 = CONN_SRAM1_A13, IO_IS = emc_addr[16]
389    PORT A14 = CONN_SRAM1_A14, IO_IS = emc_addr[15]
390    PORT A15 = CONN_SRAM1_A15, IO_IS = emc_addr[14]
391    PORT A16 = CONN_SRAM1_A16, IO_IS = emc_addr[13]
392    PORT A17 = CONN_SRAM1_A17, IO_IS = emc_addr[12]
393    PORT A18 = CONN_SRAM1_A18, IO_IS = emc_addr[11]
394
395    PORT BEN0 = CONN_SRAM1_BEN0, IO_IS = emc_ben[3]
396    PORT BEN1 = CONN_SRAM1_BEN1, IO_IS = emc_ben[2]
397    PORT BEN2 = CONN_SRAM1_BEN2, IO_IS = emc_ben[1]
398    PORT BEN3 = CONN_SRAM1_BEN3, IO_IS = emc_ben[0]
399    PORT WEN = CONN_SRAM1_WEN, IO_IS=emc_wen
400
401    PORT D0 = CONN_SRAM1_D0, IO_IS = emc_data[31]
402    PORT D1 = CONN_SRAM1_D1, IO_IS = emc_data[30]
403    PORT D2 = CONN_SRAM1_D2, IO_IS = emc_data[29]
404    PORT D3 = CONN_SRAM1_D3, IO_IS = emc_data[28]
405    PORT D4 = CONN_SRAM1_D4, IO_IS = emc_data[27]
406    PORT D5 = CONN_SRAM1_D5, IO_IS = emc_data[26]
407    PORT D6 = CONN_SRAM1_D6,  IO_IS = emc_data[25]
408    PORT D7 = CONN_SRAM1_D7, IO_IS = emc_data[24]
409    PORT D8 = CONN_SRAM1_D8, IO_IS = emc_data[23]
410    PORT D9 = CONN_SRAM1_D9, IO_IS = emc_data[22]
411    PORT D10 = CONN_SRAM1_D10, IO_IS = emc_data[21]
412    PORT D11 = CONN_SRAM1_D11, IO_IS = emc_data[20]
413    PORT D12 = CONN_SRAM1_D12, IO_IS = emc_data[19]
414    PORT D13 = CONN_SRAM1_D13, IO_IS = emc_data[18]
415    PORT D14 = CONN_SRAM1_D14, IO_IS = emc_data[17]
416    PORT D15 = CONN_SRAM1_D15, IO_IS = emc_data[16]
417    PORT D16 = CONN_SRAM1_D16, IO_IS = emc_data[15]
418    PORT D17 = CONN_SRAM1_D17, IO_IS = emc_data[14]
419    PORT D18 = CONN_SRAM1_D18, IO_IS = emc_data[13]
420    PORT D19 = CONN_SRAM1_D19, IO_IS = emc_data[12]
421    PORT D20 = CONN_SRAM1_D20, IO_IS = emc_data[11]
422    PORT D21 = CONN_SRAM1_D21, IO_IS = emc_data[10]
423    PORT D22 = CONN_SRAM1_D22, IO_IS = emc_data[9]
424    PORT D23 = CONN_SRAM1_D23, IO_IS = emc_data[8]
425    PORT D24 = CONN_SRAM1_D24, IO_IS = emc_data[7]
426    PORT D25 = CONN_SRAM1_D25, IO_IS = emc_data[6]
427    PORT D26 = CONN_SRAM1_D26, IO_IS = emc_data[5]
428    PORT D27 = CONN_SRAM1_D27, IO_IS = emc_data[4]
429    PORT D28 = CONN_SRAM1_D28, IO_IS = emc_data[3]
430    PORT D29 = CONN_SRAM1_D29, IO_IS = emc_data[2]
431    PORT D30 = CONN_SRAM1_D30, IO_IS = emc_data[1]
432    PORT D31 = CONN_SRAM1_D31, IO_IS = emc_data[0]
433
434    PORT OEN = CONN_SRAM1_OEN, IO_IS = emc_oen[0]
435    PORT ADV_LDN = CONN_SRAM1_ADV_LDN, IO_IS = emc_adv_ldn
436    PORT ZBT_CLK_OUT = CONN_SRAM1_CLK, IO_IS=EMC_CLK_OUT
437
438    PORT CKEN_PORT = CONN_SRAM1_CKEN, IO_IS = emc_cken
439    PORT CE_PORT = CONN_SRAM1_CE, IO_IS = emc_ce   
440END
441
442# This is the FPGA definition. First characterize the processor.
443BEGIN FPGA
444    ATTRIBUTE INSTANCE = fpga_0
445    ATTRIBUTE FAMILY = virtex2p
446    ATTRIBUTE  DEVICE =  XC2VP70
447    ATTRIBUTE PACKAGE =  FF1517
448    ATTRIBUTE SPEED_GRADE = -6
449    ATTRIBUTE JTAG_POSITION = 2 #SysaceCF is in position 1
450
451### Clock ###  Use the same port connection names as defined above.
452    PORT CLK_0 = CONN_GCLK0_GCLK5S, UCF_NET_STRING=("LOC=AH21", "IOSTANDARD = LVTTL")
453
454### RESET ### #Down push button
455    PORT RESET = CONN_INIT_INIT, UCF_NET_STRING=("LOC=AM16", "IOSTANDARD = LVTTL")
456
457
458
459### LED 7Seg0 ###
460    PORT SEG_LED0 = CONN_0_SEG1, UCF_NET_STRING=("LOC=AJ26", "IOSTANDARD = LVTTL")
461    PORT SEG_LED1 = CONN_0_SEG2, UCF_NET_STRING=("LOC=AH26", "IOSTANDARD = LVTTL")
462    PORT SEG_LED2 = CONN_0_SEG3, UCF_NET_STRING=("LOC=AH24", "IOSTANDARD = LVTTL")
463    PORT SEG_LED3 = CONN_0_SEG4, UCF_NET_STRING=("LOC=AH25", "IOSTANDARD = LVTTL")
464    PORT SEG_LED4 = CONN_0_SEG5, UCF_NET_STRING=("LOC=AH23", "IOSTANDARD = LVTTL")
465    PORT SEG_LED5 = CONN_0_SEG6, UCF_NET_STRING=("LOC=AG22", "IOSTANDARD = LVTTL")
466    PORT SEG_LED6 = CONN_0_SEG7, UCF_NET_STRING=("LOC=AG23", "IOSTANDARD = LVTTL")
467
468### LED 7Seg1 ###
469    PORT SEG_1_LED0 = CONN_1_SEG1, UCF_NET_STRING=("LOC=AG19", "IOSTANDARD = LVTTL")
470    PORT SEG_1_LED1 = CONN_1_SEG2, UCF_NET_STRING=("LOC=AG21", "IOSTANDARD = LVTTL")
471    PORT SEG_1_LED2 = CONN_1_SEG3, UCF_NET_STRING=("LOC=AH19", "IOSTANDARD = LVTTL")
472    PORT SEG_1_LED3 = CONN_1_SEG4, UCF_NET_STRING=("LOC=AJ19", "IOSTANDARD = LVTTL")
473    PORT SEG_1_LED4 = CONN_1_SEG5, UCF_NET_STRING=("LOC=AP12", "IOSTANDARD = LVTTL")
474    PORT SEG_1_LED5 = CONN_1_SEG6, UCF_NET_STRING=("LOC=AN13", "IOSTANDARD = LVTTL")
475    PORT SEG_1_LED6 = CONN_1_SEG7, UCF_NET_STRING=("LOC=AL15", "IOSTANDARD = LVTTL")
476
477### LED ###
478    PORT LED0 = CONN_LEDs_LED0, UCF_NET_STRING=("LOC=AJ14", "IOSTANDARD = LVTTL")
479    PORT LED1 = CONN_LEDs_LED1, UCF_NET_STRING=("LOC=AM13", "IOSTANDARD = LVTTL")
480    PORT LED2 = CONN_LEDs_LED2, UCF_NET_STRING=("LOC=AR12", "IOSTANDARD = LVTTL")
481    PORT LED3 = CONN_LEDs_LED3, UCF_NET_STRING=("LOC=AH13", "IOSTANDARD = LVTTL")
482
483### PUSH BUTTONS ###
484    PORT PUSHU = CONN_PUSHU, UCF_NET_STRING=("LOC=AJ22", "IOSTANDARD = LVTTL")
485    PORT PUSHL = CONN_PUSHL, UCF_NET_STRING=("LOC=AJ15", "IOSTANDARD = LVTTL")
486    PORT PUSHR = CONN_PUSHR, UCF_NET_STRING=("LOC=AG18", "IOSTANDARD = LVTTL")
487    PORT PUSHC = CONN_PUSHC, UCF_NET_STRING=("LOC=AG17", "IOSTANDARD = LVTTL")
488
489### UART ###
490    PORT RXD = CONN_RXD, UCF_NET_STRING=("LOC=AA29", "IOSTANDARD = LVTTL")
491    PORT TXD = CONN_TXD, UCF_NET_STRING=("LOC=AA28", "IOSTANDARD = LVTTL")
492
493### SYSACE FLASH ###
494    PORT SYSACE_CLK = sysace_clk, UCF_NET_STRING=("LOC=N20", "IOSTANDARD = LVTTL") # Input CLK
495# PORT SYSACE_CLK_OE_N = sysace_clk_oe_n, UCF_NET_STRING=("LOC= ", "IOSTANDARD = LVTTL")
496    PORT MPA00 = sysace_mpa_0, UCF_NET_STRING=("LOC=N18", "IOSTANDARD = LVTTL")
497    PORT MPA01 = sysace_mpa_1, UCF_NET_STRING=("LOC=N17", "IOSTANDARD = LVTTL")
498    PORT MPA02 = sysace_mpa_2, UCF_NET_STRING=("LOC=M14", "IOSTANDARD = LVTTL")
499    PORT MPA03 = sysace_mpa_3, UCF_NET_STRING=("LOC=M16", "IOSTANDARD = LVTTL")
500    PORT MPA04 = sysace_mpa_4, UCF_NET_STRING=("LOC=G11", "IOSTANDARD = LVTTL")
501    PORT MPA05 = sysace_mpa_5, UCF_NET_STRING=("LOC=E11", "IOSTANDARD = LVTTL")
502    PORT MPA06 = sysace_mpa_6, UCF_NET_STRING=("LOC=F11", "IOSTANDARD = LVTTL")
503    PORT MPD00 = sysace_mpd_0, UCF_NET_STRING=("LOC=M17", "IOSTANDARD = LVTTL")
504    PORT MPD01 = sysace_mpd_1, UCF_NET_STRING=("LOC=L13", "IOSTANDARD = LVTTL")
505    PORT MPD02 = sysace_mpd_2, UCF_NET_STRING=("LOC=K14", "IOSTANDARD = LVTTL")
506    PORT MPD03 = sysace_mpd_3, UCF_NET_STRING=("LOC=L12", "IOSTANDARD = LVTTL")
507    PORT MPD04 = sysace_mpd_4, UCF_NET_STRING=("LOC=J14", "IOSTANDARD = LVTTL")
508    PORT MPD05 = sysace_mpd_5, UCF_NET_STRING=("LOC=K10", "IOSTANDARD = LVTTL")
509    PORT MPD06 = sysace_mpd_6, UCF_NET_STRING=("LOC=J10", "IOSTANDARD = LVTTL")
510    PORT MPD07 = sysace_mpd_7, UCF_NET_STRING=("LOC=K12", "IOSTANDARD = LVTTL")
511    PORT MPD08 = sysace_mpd_8, UCF_NET_STRING=("LOC=H10", "IOSTANDARD = LVTTL")
512    PORT MPD09 = sysace_mpd_9, UCF_NET_STRING=("LOC=J12", "IOSTANDARD = LVTTL")
513    PORT MPD10 = sysace_mpd_10, UCF_NET_STRING=("LOC=G10", "IOSTANDARD = LVTTL")
514    PORT MPD11 = sysace_mpd_11, UCF_NET_STRING=("LOC=K11", "IOSTANDARD = LVTTL")
515    PORT MPD12 = sysace_mpd_12, UCF_NET_STRING=("LOC=F10", "IOSTANDARD = LVTTL")
516    PORT MPD13 = sysace_mpd_13, UCF_NET_STRING=("LOC=J11", "IOSTANDARD = LVTTL")
517    PORT MPD14 = sysace_mpd_14, UCF_NET_STRING=("LOC=H11", "IOSTANDARD = LVTTL")
518    PORT MPD15 = sysace_mpd_15, UCF_NET_STRING=("LOC=H12", "IOSTANDARD = LVTTL")
519    PORT MPCE  = sysace_mpce, UCF_NET_STRING=("LOC=C10", "IOSTANDARD = LVTTL")
520    PORT MPOE  = sysace_mpoe, UCF_NET_STRING=("LOC=M15", "IOSTANDARD = LVTTL")
521    PORT MPWE  = sysace_mpwe, UCF_NET_STRING=("LOC=M13", "IOSTANDARD = LVTTL")
522    PORT MPIRQ = sysace_mpirq, UCF_NET_STRING=("LOC=E10", "IOSTANDARD = LVTTL")
523
524
525# FPGA BOARD EEPROM Serial Number and Memory interface
526    PORT DQ0 = EEPROM_0_DQ0, UCF_NET_STRING=("LOC=AB28", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
527
528# 10/100 Ethernet MAC
529    PORT PHY_SLW0   = phy_slew0,     UCF_NET_STRING=("LOC=H20", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
530    PORT PHY_SLW1   = phy_slew1,     UCF_NET_STRING=("LOC=J22", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
531    PORT PHY_RESET  = phy_rst_n,     UCF_NET_STRING=("LOC=J27", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
532    PORT PHY_MDINT  = phy_mii_int_n, UCF_NET_STRING=("LOC=G27", "IOSTANDARD = LVTTL")
533    PORT PHY_CRS    = phy_crs,       UCF_NET_STRING=("LOC=D29", "IOSTANDARD = LVTTL")
534    PORT PHY_COL    = phy_col,       UCF_NET_STRING=("LOC=J26", "IOSTANDARD = LVTTL")
535    PORT PHY_TXD3   = phy_tx_data_3, UCF_NET_STRING=("LOC=G26", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
536    PORT PHY_TXD2   = phy_tx_data_2, UCF_NET_STRING=("LOC=D26", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
537    PORT PHY_TXD1   = phy_tx_data_1, UCF_NET_STRING=("LOC=H23", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
538    PORT PHY_TXD0   = phy_tx_data_0, UCF_NET_STRING=("LOC=D22", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
539    PORT PHY_TX_EN  = phy_tx_en,     UCF_NET_STRING=("LOC=H22", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
540    PORT PHY_TX_CLK = phy_tx_clk,    UCF_NET_STRING=("LOC=F20", "IOSTANDARD = LVTTL")
541    PORT PHY_TX_ER  = phy_tx_er,     UCF_NET_STRING=("LOC=H26", "IOSTANDARD = LVTTL")
542    PORT PHY_RX_ER  = phy_rx_er,     UCF_NET_STRING=("LOC=F21", "IOSTANDARD = LVTTL")
543    PORT PHY_RX_CLK = phy_rx_clk,    UCF_NET_STRING=("LOC=E24", "IOSTANDARD = LVTTL")
544    PORT PHY_RX_DV  = phy_dv,        UCF_NET_STRING=("LOC=F22", "IOSTANDARD = LVTTL")
545    PORT PHY_RXD0   = phy_rx_data_0, UCF_NET_STRING=("LOC=C22", "IOSTANDARD = LVTTL")
546    PORT PHY_RXD1   = phy_rx_data_1, UCF_NET_STRING=("LOC=E21", "IOSTANDARD = LVTTL")
547    PORT PHY_RXD2   = phy_rx_data_2, UCF_NET_STRING=("LOC=C21", "IOSTANDARD = LVTTL")
548    PORT PHY_RXD3   = phy_rx_data_3, UCF_NET_STRING=("LOC=D23", "IOSTANDARD = LVTTL")
549    PORT PHY_MDC    = phy_mii_clk,   UCF_NET_STRING=("LOC=J24", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
550    PORT PHY_MDIO   = phy_mii_data,  UCF_NET_STRING=("LOC=C23", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
551
552# 4 Dip Switchs
553    PORT SW_0 = SW_0, UCF_NET_STRING=("LOC=Y27", "IOSTANDARD = LVTTL")
554    PORT SW_1 = SW_1, UCF_NET_STRING=("LOC=Y28", "IOSTANDARD = LVTTL")
555    PORT SW_2 = SW_2, UCF_NET_STRING=("LOC=AA27", "IOSTANDARD = LVTTL")
556    PORT SW_3 = SW_3, UCF_NET_STRING=("LOC=Y29", "IOSTANDARD = LVTTL")
557
558### SRAM0_256Kx32 ###
559    PORT SRAM0_OEN = CONN_SRAM0_OEN, UCF_NET_STRING=("LOC=AP15", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
560    PORT SRAM0_ADV_LDN = CONN_SRAM0_ADV_LDN, UCF_NET_STRING=("LOC=AP14", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
561    PORT SRAM0_CLOCK = CONN_SRAM0_CLK, UCF_NET_STRING=("LOC=AR15", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 16")
562    PORT SRAM0_CKEN = CONN_SRAM0_CKEN, UCF_NET_STRING=("LOC=AH14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 8")
563    PORT SRAM0_CE = CONN_SRAM0_CE, UCF_NET_STRING=("LOC=AP11", "IOSTANDARD = LVTTL")
564    PORT SRAM0_BEN_0 = CONN_SRAM0_BEN0,  UCF_NET_STRING=("LOC=AP16", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
565    PORT SRAM0_BEN_1 = CONN_SRAM0_BEN1,  UCF_NET_STRING=("LOC=AR17", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
566    PORT SRAM0_BEN_2 = CONN_SRAM0_BEN2,  UCF_NET_STRING=("LOC=AN14", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
567    PORT SRAM0_BEN_3 = CONN_SRAM0_BEN3,  UCF_NET_STRING=("LOC=AT15", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
568    PORT SRAM0_WEN = CONN_SRAM0_WEN, UCF_NET_STRING=("LOC=AN15", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
569
570    PORT SRAM0_A0 = CONN_SRAM0_A0,   UCF_NET_STRING=("LOC=AL16", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
571    PORT SRAM0_A1 = CONN_SRAM0_A1,   UCF_NET_STRING=("LOC=AH15", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
572    PORT SRAM0_A2 = CONN_SRAM0_A2,   UCF_NET_STRING=("LOC=AL14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
573    PORT SRAM0_A3 = CONN_SRAM0_A3,   UCF_NET_STRING=("LOC=AM15", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
574    PORT SRAM0_A4 = CONN_SRAM0_A4,   UCF_NET_STRING=("LOC=AM14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
575    PORT SRAM0_A5 = CONN_SRAM0_A5,   UCF_NET_STRING=("LOC=AT9", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
576    PORT SRAM0_A6 = CONN_SRAM0_A6,   UCF_NET_STRING=("LOC=AU11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
577    PORT SRAM0_A7 = CONN_SRAM0_A7,   UCF_NET_STRING=("LOC=AN11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
578    PORT SRAM0_A8 = CONN_SRAM0_A8,   UCF_NET_STRING=("LOC=AN17", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
579    PORT SRAM0_A9 = CONN_SRAM0_A9,   UCF_NET_STRING=("LOC=AH16", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
580    PORT SRAM0_A10 = CONN_SRAM0_A10,   UCF_NET_STRING=("LOC=AR16", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
581    PORT SRAM0_A11 = CONN_SRAM0_A11,   UCF_NET_STRING=("LOC=AU15", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
582    PORT SRAM0_A12 = CONN_SRAM0_A12,   UCF_NET_STRING=("LOC=AP18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
583    PORT SRAM0_A13 = CONN_SRAM0_A13,   UCF_NET_STRING=("LOC=AJ18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
584    PORT SRAM0_A14 = CONN_SRAM0_A14,   UCF_NET_STRING=("LOC=AM17", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
585    PORT SRAM0_A15 = CONN_SRAM0_A15,   UCF_NET_STRING=("LOC=AM18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
586    PORT SRAM0_A16 = CONN_SRAM0_A16,   UCF_NET_STRING=("LOC=AK16", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
587    PORT SRAM0_A17 = CONN_SRAM0_A17,   UCF_NET_STRING=("LOC=AU14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
588    PORT SRAM0_A18 = CONN_SRAM0_A18,   UCF_NET_STRING=("LOC=AT13", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
589
590    PORT SRAM0_D0 = CONN_SRAM0_D0,   UCF_NET_STRING=("LOC=AU19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
591    PORT SRAM0_D1 = CONN_SRAM0_D1,   UCF_NET_STRING=("LOC=AH18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
592    PORT SRAM0_D2 = CONN_SRAM0_D2,   UCF_NET_STRING=("LOC=AP19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
593    PORT SRAM0_D3 = CONN_SRAM0_D3,   UCF_NET_STRING=("LOC=AT19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
594    PORT SRAM0_D4 = CONN_SRAM0_D4,   UCF_NET_STRING=("LOC=AN18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
595    PORT SRAM0_D5 = CONN_SRAM0_D5,   UCF_NET_STRING=("LOC=AR19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
596    PORT SRAM0_D6 = CONN_SRAM0_D6,   UCF_NET_STRING=("LOC=AJ17", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
597    PORT SRAM0_D7 = CONN_SRAM0_D7,   UCF_NET_STRING=("LOC=AT18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
598    PORT SRAM0_D8 = CONN_SRAM0_D8,   UCF_NET_STRING=("LOC=AM19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
599    PORT SRAM0_D9 = CONN_SRAM0_D9,   UCF_NET_STRING=("LOC=AL19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
600    PORT SRAM0_D10 = CONN_SRAM0_D10,   UCF_NET_STRING=("LOC=AK18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
601    PORT SRAM0_D11 = CONN_SRAM0_D11,   UCF_NET_STRING=("LOC=AL18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
602    PORT SRAM0_D12 = CONN_SRAM0_D12,   UCF_NET_STRING=("LOC=AU17", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
603    PORT SRAM0_D13 = CONN_SRAM0_D13,   UCF_NET_STRING=("LOC=AR18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
604    PORT SRAM0_D14 = CONN_SRAM0_D14,   UCF_NET_STRING=("LOC=AU18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
605    PORT SRAM0_D15 = CONN_SRAM0_D15,   UCF_NET_STRING=("LOC=AN19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
606    PORT SRAM0_D16 = CONN_SRAM0_D16,   UCF_NET_STRING=("LOC=AK12", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
607    PORT SRAM0_D17 = CONN_SRAM0_D17,   UCF_NET_STRING=("LOC=AL12", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
608    PORT SRAM0_D18 = CONN_SRAM0_D18,   UCF_NET_STRING=("LOC=AK14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
609    PORT SRAM0_D19 = CONN_SRAM0_D19,   UCF_NET_STRING=("LOC=AR14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
610    PORT SRAM0_D20 = CONN_SRAM0_D20,   UCF_NET_STRING=("LOC=AL11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
611    PORT SRAM0_D21 = CONN_SRAM0_D21,   UCF_NET_STRING=("LOC=AT11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
612    PORT SRAM0_D22 = CONN_SRAM0_D22,   UCF_NET_STRING=("LOC=AU10", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
613    PORT SRAM0_D23 = CONN_SRAM0_D23,   UCF_NET_STRING=("LOC=AR11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
614    PORT SRAM0_D24 = CONN_SRAM0_D24,   UCF_NET_STRING=("LOC=AR13", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
615    PORT SRAM0_D25 = CONN_SRAM0_D25,   UCF_NET_STRING=("LOC=AL13", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
616    PORT SRAM0_D26 = CONN_SRAM0_D26,   UCF_NET_STRING=("LOC=AJ13", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
617    PORT SRAM0_D27 = CONN_SRAM0_D27,   UCF_NET_STRING=("LOC=AM10", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
618    PORT SRAM0_D28 = CONN_SRAM0_D28,   UCF_NET_STRING=("LOC=AJ12", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
619    PORT SRAM0_D29 = CONN_SRAM0_D29,   UCF_NET_STRING=("LOC=AM11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
620    PORT SRAM0_D30 = CONN_SRAM0_D30,   UCF_NET_STRING=("LOC=AL10", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
621    PORT SRAM0_D31 = CONN_SRAM0_D31,   UCF_NET_STRING=("LOC=AT10", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
622
623
624### SRAM1_256Kx32 ###
625
626    PORT SRAM1_OEN = CONN_SRAM1_OEN, UCF_NET_STRING=("LOC=AP25", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
627    PORT SRAM1_ADV_LDN = CONN_SRAM1_ADV_LDN, UCF_NET_STRING=("LOC=AU26", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
628    PORT SRAM1_CLOCK = CONN_SRAM1_CLK, UCF_NET_STRING=("LOC=AP24", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 16")
629    PORT SRAM1_CKEN = CONN_SRAM1_CKEN, UCF_NET_STRING=("LOC=AR25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 8")
630    PORT SRAM1_BEN_0 = CONN_SRAM1_BEN0,  UCF_NET_STRING=("LOC=AP26", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
631    PORT SRAM1_BEN_1 = CONN_SRAM1_BEN1,  UCF_NET_STRING=("LOC=AN29", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
632    PORT SRAM1_BEN_2 = CONN_SRAM1_BEN2,  UCF_NET_STRING=("LOC=AR23", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
633    PORT SRAM1_BEN_3 = CONN_SRAM1_BEN3,  UCF_NET_STRING=("LOC=AT25", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
634    PORT SRAM1_WEN = CONN_SRAM1_WEN, UCF_NET_STRING=("LOC=AM24", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
635    PORT SRAM1_CE = CONN_SRAM1_CE, UCF_NET_STRING=("LOC=AM23", "IOSTANDARD = LVTTL")
636
637    PORT SRAM1_A0 = CONN_SRAM1_A0, UCF_NET_STRING=("LOC=AK25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
638    PORT SRAM1_A1 = CONN_SRAM1_A1, UCF_NET_STRING=("LOC=AK24", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
639    PORT SRAM1_A2 = CONN_SRAM1_A2, UCF_NET_STRING=("LOC=AU25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
640    PORT SRAM1_A3 = CONN_SRAM1_A3, UCF_NET_STRING=("LOC=AR24", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
641    PORT SRAM1_A4 = CONN_SRAM1_A4, UCF_NET_STRING=("LOC=AN23", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
642    PORT SRAM1_A5 = CONN_SRAM1_A5, UCF_NET_STRING=("LOC=AH22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
643    PORT SRAM1_A6 = CONN_SRAM1_A6, UCF_NET_STRING=("LOC=AL23", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
644    PORT SRAM1_A7 = CONN_SRAM1_A7, UCF_NET_STRING=("LOC=AN22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
645    PORT SRAM1_A8 = CONN_SRAM1_A8, UCF_NET_STRING=("LOC=AT28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
646    PORT SRAM1_A9 = CONN_SRAM1_A9, UCF_NET_STRING=("LOC=AR28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
647    PORT SRAM1_A10 = CONN_SRAM1_A10, UCF_NET_STRING=("LOC=AT26", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
648    PORT SRAM1_A11 = CONN_SRAM1_A11, UCF_NET_STRING=("LOC=AL28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
649    PORT SRAM1_A12 = CONN_SRAM1_A12, UCF_NET_STRING=("LOC=AK29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
650    PORT SRAM1_A13 = CONN_SRAM1_A13, UCF_NET_STRING=("LOC=AR26", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
651    PORT SRAM1_A14 = CONN_SRAM1_A14, UCF_NET_STRING=("LOC=AH27", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
652    PORT SRAM1_A15 = CONN_SRAM1_A15, UCF_NET_STRING=("LOC=AU29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
653    PORT SRAM1_A16 = CONN_SRAM1_A16, UCF_NET_STRING=("LOC=AP29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
654    PORT SRAM1_A17 = CONN_SRAM1_A17, UCF_NET_STRING=("LOC=AJ23", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
655    PORT SRAM1_A18 = CONN_SRAM1_A18, UCF_NET_STRING=("LOC=AP28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
656
657    PORT SRAM1_D0 = CONN_SRAM1_D0, UCF_NET_STRING=("LOC=AT31", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
658    PORT SRAM1_D1 = CONN_SRAM1_D1, UCF_NET_STRING=("LOC=AT30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
659    PORT SRAM1_D2 = CONN_SRAM1_D2, UCF_NET_STRING=("LOC=AL30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
660    PORT SRAM1_D3 = CONN_SRAM1_D3, UCF_NET_STRING=("LOC=AJ28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
661    PORT SRAM1_D4 = CONN_SRAM1_D4, UCF_NET_STRING=("LOC=AK28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
662    PORT SRAM1_D5 = CONN_SRAM1_D5, UCF_NET_STRING=("LOC=AM30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
663    PORT SRAM1_D6 = CONN_SRAM1_D6, UCF_NET_STRING=("LOC=AR29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
664    PORT SRAM1_D7 = CONN_SRAM1_D7, UCF_NET_STRING=("LOC=AL29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
665    PORT SRAM1_D8 = CONN_SRAM1_D8, UCF_NET_STRING=("LOC=AL27", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
666    PORT SRAM1_D9 = CONN_SRAM1_D9, UCF_NET_STRING=("LOC=AM25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
667    PORT SRAM1_D10 = CONN_SRAM1_D10, UCF_NET_STRING=("LOC=AR31", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
668    PORT SRAM1_D11 = CONN_SRAM1_D11, UCF_NET_STRING=("LOC=AM29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
669    PORT SRAM1_D12 = CONN_SRAM1_D12, UCF_NET_STRING=("LOC=AN30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
670    PORT SRAM1_D13 = CONN_SRAM1_D13, UCF_NET_STRING=("LOC=AL25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
671    PORT SRAM1_D14 = CONN_SRAM1_D14, UCF_NET_STRING=("LOC=AM28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
672    PORT SRAM1_D15 = CONN_SRAM1_D15, UCF_NET_STRING=("LOC=AU30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
673    PORT SRAM1_D16 = CONN_SRAM1_D16, UCF_NET_STRING=("LOC=AR22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
674    PORT SRAM1_D17 = CONN_SRAM1_D17, UCF_NET_STRING=("LOC=AM22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
675    PORT SRAM1_D18 = CONN_SRAM1_D18, UCF_NET_STRING=("LOC=AT23", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
676    PORT SRAM1_D19 = CONN_SRAM1_D19, UCF_NET_STRING=("LOC=AU22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
677    PORT SRAM1_D20 = CONN_SRAM1_D20, UCF_NET_STRING=("LOC=AT22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
678    PORT SRAM1_D21 = CONN_SRAM1_D21, UCF_NET_STRING=("LOC=AL21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
679    PORT SRAM1_D22 = CONN_SRAM1_D22, UCF_NET_STRING=("LOC=AU21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
680    PORT SRAM1_D23 = CONN_SRAM1_D23, UCF_NET_STRING=("LOC=AP21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
681    PORT SRAM1_D24 = CONN_SRAM1_D24, UCF_NET_STRING=("LOC=AT21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
682    PORT SRAM1_D25 = CONN_SRAM1_D25, UCF_NET_STRING=("LOC=AN21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
683    PORT SRAM1_D26 = CONN_SRAM1_D26, UCF_NET_STRING=("LOC=AK22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
684    PORT SRAM1_D27 = CONN_SRAM1_D27, UCF_NET_STRING=("LOC=AP22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
685    PORT SRAM1_D28 = CONN_SRAM1_D28, UCF_NET_STRING=("LOC=AR21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
686    PORT SRAM1_D29 = CONN_SRAM1_D29, UCF_NET_STRING=("LOC=AM20", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
687    PORT SRAM1_D30 = CONN_SRAM1_D30, UCF_NET_STRING=("LOC=AK21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
688    PORT SRAM1_D31 = CONN_SRAM1_D31, UCF_NET_STRING=("LOC=AP20", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
689
690    #USER I/O Board in Slot 1
691    #LCD SPI interface
692    PORT user_ioboard_slot1_sdi = user_ioboard_slot1_sdi, UCF_NET_STRING=("LOC=W4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
693    PORT userio_board_slot1_scl = userio_board_slot1_scl, UCF_NET_STRING=("LOC=V3", "SLEW=SLOW", "IOSTANDARD=LVTTL")
694    PORT userio_board_slot1_resetlcd = userio_board_slot1_resetlcd, UCF_NET_STRING=("LOC=V5", "SLEW=SLOW", "IOSTANDARD=LVTTL")
695    PORT userio_board_slot1_cs = userio_board_slot1_cs, UCF_NET_STRING=("LOC=V8", "SLEW=SLOW", "IOSTANDARD=LVTTL")
696
697    #Buzzer output
698    PORT userio_board_slot1_buzzer = userio_board_slot1_buzzer, UCF_NET_STRING=("LOC=P3", "SLEW=SLOW", "IOSTANDARD=LVTTL")
699
700    #Trackball I/O
701    PORT userio_board_slot1_trackball_yscn = userio_board_slot1_trackball_yscn, UCF_NET_STRING=("LOC=T3", "SLEW=SLOW", "IOSTANDARD=LVTTL")
702    PORT userio_board_slot1_trackball_sel1 = userio_board_slot1_trackball_sel1, UCF_NET_STRING=("LOC=U4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
703    PORT userio_board_slot1_trackball_xscn = userio_board_slot1_trackball_xscn, UCF_NET_STRING=("LOC=V4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
704    PORT userio_board_slot1_trackball_sel2 = userio_board_slot1_trackball_sel2, UCF_NET_STRING=("LOC=V6", "SLEW=SLOW", "IOSTANDARD=LVTTL")
705    PORT userio_board_slot1_trackball_oyn = userio_board_slot1_trackball_oyn, UCF_NET_STRING=("LOC=T11", "SLEW=SLOW", "IOSTANDARD=LVTTL")
706    PORT userio_board_slot1_trackball_oy = userio_board_slot1_trackball_oy, UCF_NET_STRING=("LOC=U9", "SLEW=SLOW", "IOSTANDARD=LVTTL")
707    PORT userio_board_slot1_trackball_oxn = userio_board_slot1_trackball_oxn, UCF_NET_STRING=("LOC=U10", "SLEW=SLOW", "IOSTANDARD=LVTTL")
708    PORT userio_board_slot1_trackball_ox = userio_board_slot1_trackball_ox, UCF_NET_STRING=("LOC=V9", "SLEW=SLOW", "IOSTANDARD=LVTTL")
709
710    #Eight LEDs
711    PORT userio_board_slot1_leds_0 = userio_board_slot1_leds_0, UCF_NET_STRING=("LOC=P10", "SLEW=SLOW", "IOSTANDARD=LVTTL")
712    PORT userio_board_slot1_leds_1 = userio_board_slot1_leds_1, UCF_NET_STRING=("LOC=P8", "SLEW=SLOW", "IOSTANDARD=LVTTL")
713    PORT userio_board_slot1_leds_2 = userio_board_slot1_leds_2, UCF_NET_STRING=("LOC=P1", "SLEW=SLOW", "IOSTANDARD=LVTTL")
714    PORT userio_board_slot1_leds_3 = userio_board_slot1_leds_3, UCF_NET_STRING=("LOC=P2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
715    PORT userio_board_slot1_leds_4 = userio_board_slot1_leds_4, UCF_NET_STRING=("LOC=N5", "SLEW=SLOW", "IOSTANDARD=LVTTL")
716    PORT userio_board_slot1_leds_5 = userio_board_slot1_leds_5, UCF_NET_STRING=("LOC=M3", "SLEW=SLOW", "IOSTANDARD=LVTTL")
717    PORT userio_board_slot1_leds_6 = userio_board_slot1_leds_6, UCF_NET_STRING=("LOC=N6", "SLEW=SLOW", "IOSTANDARD=LVTTL")
718    PORT userio_board_slot1_leds_7 = userio_board_slot1_leds_7, UCF_NET_STRING=("LOC=L6", "SLEW=SLOW", "IOSTANDARD=LVTTL")
719
720    #DIP switch
721    PORT userio_board_slot1_dip_switch_0 = userio_board_slot1_dip_switch_0, UCF_NET_STRING=("LOC=K2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
722    PORT userio_board_slot1_dip_switch_1 = userio_board_slot1_dip_switch_1, UCF_NET_STRING=("LOC=K1", "SLEW=SLOW", "IOSTANDARD=LVTTL")
723    PORT userio_board_slot1_dip_switch_2 = userio_board_slot1_dip_switch_2, UCF_NET_STRING=("LOC=P4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
724    PORT userio_board_slot1_dip_switch_3 = userio_board_slot1_dip_switch_3, UCF_NET_STRING=("LOC=N3", "SLEW=SLOW", "IOSTANDARD=LVTTL")
725
726    #Six small push buttons
727    PORT userio_board_slot1_buttons_small_0 = userio_board_slot1_buttons_small_0, UCF_NET_STRING=("LOC=M2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
728    PORT userio_board_slot1_buttons_small_1 = userio_board_slot1_buttons_small_1, UCF_NET_STRING=("LOC=R11", "SLEW=SLOW", "IOSTANDARD=LVTTL")
729    PORT userio_board_slot1_buttons_small_2 = userio_board_slot1_buttons_small_2, UCF_NET_STRING=("LOC=N2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
730    PORT userio_board_slot1_buttons_small_3 = userio_board_slot1_buttons_small_3, UCF_NET_STRING=("LOC=M7", "SLEW=SLOW", "IOSTANDARD=LVTTL")
731    PORT userio_board_slot1_buttons_small_4 = userio_board_slot1_buttons_small_4, UCF_NET_STRING=("LOC=L5", "SLEW=SLOW", "IOSTANDARD=LVTTL")
732    PORT userio_board_slot1_buttons_small_5 = userio_board_slot1_buttons_small_5, UCF_NET_STRING=("LOC=L4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
733
734    #Two big push buttons
735    PORT userio_board_slot1_buttons_big_0 = userio_board_slot1_buttons_big_0, UCF_NET_STRING=("LOC=R1, "SLEW=SLOW", "IOSTANDARD=LVTTL")
736    PORT userio_board_slot1_buttons_big_1 = userio_board_slot1_buttons_big_1, UCF_NET_STRING=("LOC=R2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
737
738END
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